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參數(shù)資料
| 型號(hào)： | mPD784036 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/8-BIT SINGLE-CHIP MICROCONTROLLER |
| 中文描述： | 16/8-BIT單片機(jī) |
| 文件頁(yè)數(shù)： | 28/90頁(yè) |
| 文件大小： | 377K |
| 代理商： | MPD784036 |
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μ
PD784031
28
Table 8-1. Port Functions
8.2 Clock Generator
A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency
divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed
operation is not necessary.
Figure 8-2. Block Diagram of Clock Generator
X1
X2
f
XX
/2
f
XX
f
CLK
CPU
Peripheral circuits
Oscillator
UART/IOE
INTP0 noise eliminator
Oscillation settling timer
S
1/2
1/2
1/2
1/2
Remark
f
XX
: Oscillator frequency or external clock input
f
CLK
: Internal operating frequency
Port name
Pin
Function
Pull-up specification by software
Port 0
P00-P07
Bit-by-bit input/output setting supported
Operable as 4-bit real-time outputs
(P00-P03, P04-P07)
Capable of driving transistors
Specified as a batch for all pins placed in
input mode.
Port 1
P10-P17
Bit-by-bit input/output setting supported
Capable of driving LEDs
Specified as a batch for all pins placed in
input mode.
Port 2
P20-P27
Input port
Specified for the 6 bits (P22-P27) as a batch.
Port 3
P30-P37
Bit-by-bit input/output setting supported
Specified as a batch for all pins placed in
input mode.
Port 6
P60-P63
Output-only port
Specified as a batch for all pins placed in
P66, P67
Bit-by-bit input/output setting supported
input mode.
Port 7
P70-P77
Bit-by-bit input/output setting supported
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