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參數(shù)資料
| 型號： | mPD16650 |
| 廠商： | NEC Corp. |
| 英文描述： | 120-/128-OUTPUT TFT-LCD GATE DRIVER |
| 中文描述： | 120-/128-OUTPUT的TFT - LCD柵極驅(qū)動器 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 62K |
| 代理商： | MPD16650 |
μ
PD16650
5
CAUTIONS FOR USE
1)
Power-on sequence
To prevent latch-up disruption, the power must be switched on in the order:
V
CC
→
V
EE1
→
V
EE2
→
V
DD
→
Logic input
When witching off, reverse the order. This order must be observed also during transition.
2)
Insertion of bypass capacitors
The internal logic circuit operates at a high voltage. To make V
IH
and V
IL
immune to noise, use capacitors of
0.1
μ
F or so between supply voltages as shown below.
V
DD
V
CC
V
SS
V
EE2
0.1 F
0.1 F
0.1 F
3)
Negative voltage level shift
If it is necessary to shift the level of a negative supply voltage, shift the V
EE1
(driver supply voltage) level. The
shift should be limited to within: V
EE2
≤
V
EE1
≤
V
EE2
+ 10 V
Note that shifting the V
EE1
level results in the ON-state output resistance and output fall time ratings being
changed.
4)
Handling the V
EE1
and V
EE2
driver negative supply voltage pins
For applications in which a negative supply voltage level is not shifted, connect the V
EE1
pin (driver supply voltage)
to the V
EE2
pin (logic supply voltage) outside the TCP. Fix all unused input pins to the V
EE2
level.
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