- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26839 > MPC99J93FAR2 (FREESCALE SEMICONDUCTOR INC) PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 PDF資料下載
參數(shù)資料
| 型號： | MPC99J93FAR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 213K |
| 代理商： | MPC99J93FAR2 |
MPC99J93
MOTOROLA TIMING SOLUTIONS
5
Table 5. AC Characteristics (VCC =3.3V ± 5%, TA =--40°Cto+85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Reference Frequency
÷4 feedback
50
90
MHz
PLL locked
fVCO
VCO Frequency Rangeb
÷4 feedback
200
360
MHz
fMAX
Output Frequency
QA[1:0]
QB[2:0]
50
100
90
180
MHz
PLL locked
frefDC
Reference Input Duty Cycle
25
75
%
t()
Propagation Delay
SPO, static phase offsetc
CLK0, CLK1 to any Q
-0.15
0.9
+0.17
1.8
ns
PLL_EN=1
PLL_EN=0
VPP
Differential input voltaged
(peak-to-peak)
0.25
1.3
V
VCMR
Differential input crosspoint voltagee
VCC-1.7
VCC-0.3
V
tsk(O)
Output-to-output Skew
within QA[2:0] or QB[1:0]
within device
50
80
ps
per/cycle
Rate of change of period
QA[1:0]f
QB[2:0]f
QA[1:0]g
QB[2:0]g
20
10
200
100
50
25
400
200
ps
DC
Output Duty Cycle
45
50
55
%
tJIT(CC)
Cycle-to-Cycle Jitter
RMS (1 σ)
25
ps
tLOCK
Maximum PLL Lock Time
10
ms
tr,tf
Output Rise/Fall Time
0.05
0.70
ns
20% to 80%
a. AC characteristics apply for parallel output termination of 50 to VCC - 2V.
b. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): fref =fVCO ÷ FB.
c. CLK0,CLK1toExt_FB.
d. VPP is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew. Ap-
plicable to CLK0, CLK1 and Ext_FB.
e. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the V PP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the SPO, device and part-to-
part skew. Applicable to CLK0, CLK1 and Ext_FB.
f. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change
per cycle is averaged over the clock switch excursion.
g. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (±180_). Delta period change per
cycle is averaged over the clock switch excursion.
相關PDF資料 |
PDF描述 |
|---|---|
| MPDU281-2.0 | SILICON DELAY LINE, PDIP16 |
| MPDU282-2.0 | SILICON DELAY LINE, PDIP16 |
| MPDU482-4.5 | SILICON DELAY LINE, PDIP24 |
| MPDU882-4.5 | SILICON DELAY LINE, PDIP40 |
| MPDU482S-0.25 | SILICON DELAY LINE, DSO24 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPCA06 | 制造商:Motorola Inc 功能描述: |
| MPCB-20.0-0-E563 | 制造商:TE Connectivity 功能描述:MPCB-20.0-0-E563 |
| MPCB-20.0-2 | 制造商:TE Connectivity 功能描述:MPCB-20.0-2 |
| MPCBL0001N04Q | 制造商:Intel 功能描述:KENNICOTT (NO FC, 2 X 2.0 GHZ) NO MEMORY OR HARD DRIVE, ROHS - Bulk |
| MPCBL0010N01Q | 制造商:Intel 功能描述:WAINWRIGHTBOARD - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。