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參數(shù)資料
| 型號(hào)： | MPC9993ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK DRIVER IDCS 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時(shí)鐘驅(qū)動(dòng)器，動(dòng)態(tài)時(shí)鐘開(kāi)關(guān) |
| PLL： | 帶旁路 |
| 輸入： | LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC9993 REVISION 3 JANUARY 23, 2013
2
2013 Integrated Device Technology, Inc.
MPC9993 Data Sheet
INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS) PLL CLOCK DRIVER
Figure 2. 32-Lead Pinout (Top View)
Table 1. Pin Descriptions
Pin Name
I/O
Pin Definition
CLK0, CLK0
CLK1, CLK1
LVPECL Input
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Ext_FB, Ext_FB
LVPECL Input
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
Qa0:1, Qa0:1
LVPECL Output
Differential 1x output pairs
Qb0:2, Qb0:2
LVPECL Output
Differential 2x output pairs
Inp0bad
LVCMOS Output Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output is
active HIGH and will remain HIGH until the alarm reset is asserted
Inp1bad
LVCMOS Output Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output is
active HIGH and will remain HIGH until the alarm reset is asserted
Clk_Selected
LVCMOS Output ‘0' if clock 0 is selected, ‘1' if clock 1 is selected
Alarm_Reset
LVCMOS Input
‘0' will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one-shotted”
(50 k
pullup)
Sel_Clk
LVCMOS Input
‘0' selects CLK0, ‘1' selects CLK1 (50 k
pulldown)
Manual_Override
LVCMOS Input
‘1' disables internal clock switch circuitry (50 k
pulldown)
PLL_En
LVCMOS Input
‘0' bypasses selected input reference around the phase-locked loop (50 k
pullup)
MR
LVCMOS Input
‘0' resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50 k
pullup)
VCCA
Power Supply
PLL power supply
VCC
Power Supply
Digital power supply
GNDA
Power Supply
PLL ground
GND
Power Supply
Digital ground
Qa1
Qa0
VCC
VCC_PLL
Man_Override
VCC
Inp0bad
Inp1bad
Clk_Selected
GND
Ext_FB
V
CC
Qb
0
Qb
0
Qb
1
Qb
1
Qb
2
Qb
2
V
CC
MR
Alarm_Rese
t
CLK0
Sel_Clk
CLK1
GND
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12
3
4
5
6
78
24
23
22
21
20
19
18
17
16
MPC9993
PLL_EN
Ext_FB
GND
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