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參數(shù)資料
| 型號： | MPC9991FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9991FA |
MPC9991
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
293
Table 6: PECL DC CHARACTERISTICS (VCC = 3.3V ± 5%, VEE = GND, TA = 0°C to 70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential PECL clock inputs (ECLK, ECLK and FB_IN, FB_IN)b
VPP
AC differential input voltagec
0.1
1.3
V
Differential operation
VCMR
Differential cross point voltaged
1.0
VCC-0.3
V
Differential operation
Single-ended PECL clock inputs (TCLK, VCO_SEL, PLL_EN, MR, REF_SEL, SYNC_SEL, FSEL_FB[2:0], FSEL[3:0])
VIH
Input High Voltage
TBD
VIL
Input Low Voltage
TBD
IIN
Input Current
±TBD
A
VIN = TBD or VIN = TBD
PECL clock outputs (QA[3:0], QA[3:0], QB[3:0], QB[3:0], QC[2:0], QC[2:0], QD[1:0], QD[1:0])
VOH
Output High Voltage
TBD
VCC-1.005
TBD
V
Termination 50
W to VTT
VOL
Output Low Voltage
TDB
VCC-1.705
TBD
V
Termination 50
W to VTT
Supply Current
IEE
Maximum Quiescent Supply Current
without output termination current
TBD
mA
VEE pin
ICCe
Maximum Quiescent Supply Current,
outputs terminated 50
W to VTT
TBD
mA
VCC pins
a.
AC characteristics are design targets and pending characterization.
b.
Clock inputs driven by PECL compatible signals.
c.
VPP is the minimum differential input voltage swing required to maintain AC characteristics.
d.
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
e.
ICC includes current through the output resistors (all outputs terminated to VTT).
Table 7: ECL DC CHARACTERISTICS (VEE = –3.3V ± 5%, VCC = GND, TA = 0°C to 70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Differential ECL clock inputs (ECLK, ECLK and FB_IN, FB_IN)b
VPP
Differential input voltagec
0.1
1.3
V
Differential operation
VCMR
Differential cross point voltaged
VEE+1.0
-0.3
V
Differential operation
IIN
Input Currenta
±150
A
VIN = VIL or VIN = VIH
Single-ended ECL clock inputs (TCLK, VCO_SEL, PLL_EN, MR, REF_SEL, SYNC_SEL, FSEL_FB[2:0], FSEL[3:0])
VIL
Input Voltage Low
-1.46
V
VIH
Input Voltage High
-1.14
V
IIN
Input Currente
±150
A
VIN = VIL or VIN = VIH
ECL clock outputs (QA[3:0], QA[3:0], QB[3:0], QB[3:0], QC[2:0], QC[2:0], QD[1:0], QD[1:0])
VOH
Output High Voltage
TBD
-1.005
TBD
V
Termination 50
W to VTT
VOL
Output Low Voltage
TBD
-1.705
TBD
V
Termination 50
W to VTT
Supply current and V
IEE
Maximum Quiescent Supply Current
without output termination current
TBD
mA
VEE pin
ICCf
Maximum Quiescent Supply Current,
outputs terminated 50
W to VTT
TBD
mA
VCC pins
a.
DC characteristics are design targets and pending characterization.
b.
Clock inputs driven by PECL compatible signals.
c.
VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
d.
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
e.
Input have internal pullup/pulldown resistors which affect the input current.
f.
ICC includes current through the output resistors (all outputs terminated to VTT).
2
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