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參數(shù)資料
| 型號： | MPC9893AER2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 1:12 3.3V 48-LQFP |
| 標準包裝： | 2,000 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC9893 REVISION 8 JANUARY 16, 2013
11
2013 Integrated Device Technology, Inc.
MPC9893 Data Sheet
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
Figure 13. Propagation Delay (t(), static phase
offset) Test Reference
Figure 14. Output Duty Cycle (DC)
Figure 12. Output-to-Output Skew tSK(O)
The pin-to-pin skew is defined as the worst case difference in propagation delay
between any similar delay path within a single device
VCC
VCC 2
GND
VCC
VCC 2
GND
tSK(O)
VCC
VCC 2
GND
VCC
VCC 2
GND
t()
CLK0,
CLK1
FB
The time from the PLL controlled edge to the noncontrolled edge, divided by
the time between PLL controlled edges, expressed as a percentage
VCC
VCC 2
GND
tP
T0
DC = tP/T0 x 100%
Figure 16. Cycle-to-Cycle Jitter
Figure 15. I/O Jitter
Figure 18. Output Transition Time Test Reference
tF
tR
VCC=3.3 V
2.4
0.55
TJIT() = |T0–T1mean|
CCLK0, 1
FB
The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample
of cycles
The variation in cycle time of a signal between adjacent cycles, over a random sample
of adjacent cycle pairs
TN
TJIT(CC) = |TN–TN+1|
TN+1
The deviation in cycle time of a signal with respect to the ideal period over a random
sample of cycles
TJIT(PER) = |TN–1/f0|
T0
Figure 17. Period Jitter
VCC=2.5 V
1.8
0.6
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9893FA | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 48-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9893FAR2 - Tape and Reel |
| MPC9894 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Input Redundant IDCS Clock Generator |
| MPC9894VM | 制造商:IDT from Components Direct 功能描述:IDT MPC9894VM PLL - Trays 制造商:IDT 功能描述:IDT MPC9894VM PLL |
| MPC990 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
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