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參數(shù)資料
| 型號(hào)： | MPC9865VF |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, PBGA100 |
| 封裝： | 11 X 11 MM, 1 MM PITCH, MO-192DAC-1, MAPBGA-100 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 302K |
| 代理商： | MPC9865VF |
Advanced Clock Drivers Devices
Freescale Semiconductor
5
MPC9865
OPERATION INFORMATION
Output Frequency Configuration
The MPC9865 was designed to provide the commonly
used frequencies in PowerQUICC, PowerPC and other
microprocessor systems. Table 3 lists the configuration
values that will generate those common frequencies. The
MPC9865 can generate numerous other frequencies that
may be useful in specific applications. The output frequency
(fout) of either Bank A or Bank B may be calculated by the
following equation.
fout = 2000 / N
where fout is in MHz and N = 2 * CLK_x[0:5]
This calculation is valid for all values of N from 8 to 126.
Note that N = 15 is a modified case of the configuration inputs
CLK_x[0:5]. To achieve N = 15 CLK_x[0:5] is configured to
00111 or 7.
Crystal Input Operation
TBD
Power-Up and MR Operation
Figure 2 defines the release time and the minimum pulse
length for MR pin. The MR release time is based upon the
power supply being stable and within VDD specifications. See
Table 9 for actual parameter values. The MPC9865 may be
configured after release of reset and the outputs will be stable
for use after lock indication is obtained.
Figure 2. MR Operation
Power Supply Bypassing
The MPC9865 is a mixed analog/digital product. The
architecture of the MPC9865 supports low noise signal
operation at high frequencies. In order to maintain its superior
signal quality, all VDD pins should be bypassed by
high-frequency ceramic capacitors connected to GND. If the
spectral frequencies of the internally generated switching
noise on the supply pins cross the series resonant point of an
individual bypass capacitor, its overall impedance begins to
look inductive and thus increases with increasing frequency.
The parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the noise bandwidth.
Figure 3. VCC Power Supply Bypass
Power Consumption Calculation
For unloaded outputs the power consumption of the
MPC9855 can be calculated as follows.
P = VDD * IDDBASE + nA * (VDDOA ** 2 * CPD * fA)
+ nB * (VDDOB ** 2 * CPD * fB)
where
VDD = core supply voltage
IDDBASE = base supply current
nA = number of A bank outputs (= 4)
nB = number of B bank outputs (= 4)
VDDOA = voltage supply on bank A outputs
VDDOB = voltage supply on bank B outputs
CPD = power dissipation capacitance
fA = frequency of bank A outputs
fB = frequency of bank B outputs
MR
VDD
treset_rel
treset_pulse
VDD
MPC9865
0.1
μF
22
μF
0.1
μF
15
Ω
VDD
VDDA
MPC9865
Clock Generator for PowerQUICC III
NETCOM
IDT Clock Generator for PowerQUICC III
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9865
5
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| MPC9865VM | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9865VMR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:Low Voltage PLL Intelligent Dynamic Clock (IDCS) Switch |
| MPC9893AE | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9893AER2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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