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參數(shù)資料
| 型號： | MPC97H74AE |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 1:14 3.3V 52-LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:14 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-TQFP（10x10） |
| 包裝： | 托盤 |
MPC97H74 REVISION 5 JANUARY 9, 2013
9
2013 Integrated Device Technology, Inc.
MPC97H74 Data Sheet
3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR
Power Supply Filtering
The MPC97H74 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCC_PLL power supply impacts the
device characteristics, for instance I/O jitter. The MPC97H74
provides separate power supplies for the output buffers (VCC)
and the phase-locked loop (VCC_PLL) of the device.The
purpose of this design technique is to isolate the high
switching noise digital outputs from the relatively sensitive
internal analog phase-locked loop. In a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simple but effective form of isolation is a power supply
VCC_PLL Power Supply Filter illustrates a typical power
supply filter scheme. The MPC97H74 frequency and phase
stability is most susceptible to noise with spectral content in
the 100 kHz to 20 MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop
across the series filter resistor RF. From the data sheet the
ICC_PLL current (the current sourced through the VCC_PLL
pin) is typically 5 mA (7.5 mA maximum), assuming that a
minimum of 3.02 V (VCC_PLL, minimum) must be maintained
VCC_PLL Power Supply Filter must have a resistance of
5 – 15
to meet the voltage drop criteria.
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 11. VCC_PLL Power Supply Filter, the
filter cut-off frequency is around 3-5 kHz and the noise
attenuation at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC97H74 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Figure 11. VCC_PLL Power Supply Filter
VCC_PLL
VCC
MPC97H74
10 nF
RF = 5–15
CF
33...100 nF
RF
VCC
CF = 22 F
Figure 12. CCLK MPC97H74 AC Test Reference
Pulse
Generator
Z = 50
RT = 50
Z = 50
RT = 50
Z = 50
MPC97H74 DUT
VTT
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| MPC97H74AER2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-14 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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