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參數(shù)資料
| 型號： | MPC9774FAR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 14/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 1:14 3.3V 52-LQFP |
| 標準包裝： | 1,500 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:14 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應(yīng)商設(shè)備封裝： | 52-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
MPC9774 REVISION 5 JANUARY 10, 2013
9
2013 Integrated Device Technology, Inc.
MPC9774 Data Sheet
3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR
Driving Transmission Lines
The MPC9774 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale Semiconductor
application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50
resistance to VCC 2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9774 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 8 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme
the fanout of the MPC9774 clock driver is effectively doubled
due to its capability to drive multiple lines.
Figure 8. Single versus Dual Transmission Lines
The waveform plots in Figure 9 show the simulation results
of an output driving a single line versus two lines. In both
cases the drive capability of the MPC9774 output buffer is
more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9774. The output waveform
in Figure 9 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36
series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
VL =VS (Z0 (RS + R0 + Z0))
Z0 =50 || 50
RS =36 || 36
R0 =14
VL = 3.0 (25 (18 + 17 + 25)
=1.31 V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
Figure 9. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 10 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 10. Optimized Dual Line Termination
14
In
MPC9774
Output
Buffer
RS = 36
ZO = 50
OutA
14
In
MPC9774
Output
Buffer
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
Time (ns)
Volt
age
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
14
MPC9774
Output
Buffer
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 22 = 50 || 50
25
= 25
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