- 您現(xiàn)在的位置：買賣IC網 > PDF目錄2014 > MPC9773AE (IDT, Integrated Device Technology Inc)IC PLL CLK GEN 1:12 3.3V 52-LQFP PDF資料下載
參數(shù)資料
| 型號： | MPC9773AE |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
| 標準包裝： | 160 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVPECL |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:12 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 242.5MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應商設備封裝： | 52-TQFP（10x10） |
| 包裝： | 托盤 |
MPC9773 REVISION 6 JANUARY 31, 2013
10
2013 Integrated Device Technology, Inc.
MPC9773 Data Sheet
3.3 V 1:12 LVCMOS PLL CLOCK GENERATOR
MPC9773 Individual Output Disable (Clock Stop)
Circuitry
The individual clock stop (output enable) control of the
MPC9773 allows designers, under software control, to
implement power management into the clock distribution
design. A simple serial interface and a clock stop control logic
provides a mechanism through which the MPC9773 clock
outputs can be individually stopped in the logic ‘0’ state: The
clock stop mechanism allows serial loading of a 12-bit serial
input register. This register contains one programmable clock
stop bit for 12 of the 14 output clocks. The QC0 and QFB
outputs cannot be stopped (disabled) with the serial port.
The user can program an output clock to stop (disable) by
writing logic ‘0’ to the respective stop enable bit. Likewise, the
user may programmably enable an output clock by writing
logic ‘1’ to the respective enable bit. The clock stop logic
enables or disables clock outputs during the time when the
output would normally be in logic low state, eliminating the
possibility of short or ‘runt’ clock pulses.
The user can write to the serial input register through the
STOP_DATA input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ disable/enable bits. The period of each
STOP_DATA bit equals the period of the free-running
STOP_CLK signal. The STOP_DATA serial transmission
should be timed so the MPC9773 can sample each
STOP_DATA bit with the rising edge of the free-running
STOP_CLK signal. (See Figure 5.)
Figure 5. Clock Stop Circuit Programing
STOP_CLK
STOP_DATA
START
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
相關PDF資料 |
PDF描述 |
|---|---|
| MPC9850VF | IC PLL CLOCK GENERATOR 100MAPBGA |
| MPC9855VM | IC PLL CLOCK GENERATOR 100MAPBGA |
| MPC9893AE | IC PLL CLK GEN 1:12 3.3V 48-LQFP |
| MSTM-S3-TR-19.44M | IC MOD TIMING 19.440MHZ STRAT 3 |
| MT5656RJ-92.R2 | MODEM SERIAL DATA V.92 5V |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9773AER2 | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9773FA | 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9773FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 52-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:MPC9773FAR2 - Tape and Reel |
| MPC9774 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2,5V 1:14 LVCMOS PLL CLOCK GENERATOR |
| MPC9774AE | 功能描述:時鐘發(fā)生器及支持產品 3.3V 125MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復。