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參數(shù)資料
| 型號(hào)： | MPC9772FA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 230 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 833K |
| 代理商： | MPC9772FA |
MPC9772
3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
IDT / ICS 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR
12
MPC9772 REV 6 FEBRUARY 7, 2007
Due to the statistical nature of I/O jitter a RMS value (1
σ)
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from Table 12.
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device.
Due to the frequency dependence of the static phase
maximum I/O jitter and the specified t() parameter relative to
the input reference frequency results in a precise timing
performance analysis.
In the following example calculation an I/O jitter confidence
factor of 99.7% (
± 3σ) is assumed, resulting in a worst case
timing uncertainty from the common input reference clock to
any output of –455 ps to +455 ps relative to CCLK (PLL
feedback =
÷8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 13 ps rms max., static
phase offset t() = ± 166 ps):
tSK(PP) = [-166ps...166ps] + [-250ps...250ps] +
[(13ps @ –3)...(13ps @ 3)] + tPD, LINE(FB)
tSK(PP) = [-455ps...455ps] + tPD, LINE(FB)
Figure 9. MPC9772 I/O Jitter
Figure 10. MPC9772 I/O Jitter
Figure 11. MPC9772 I/O Jitter
Driving Transmission Lines
The MPC9772 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20
the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Freescale Semiconductor
application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The
parallel technique terminates the signal at the end of the line
with a 50
resistance to VCC÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC9772 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 12
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC9772 clock driver is
effectively doubled due to its capability to drive multiple lines.
Table 12. Confidence Factor CF
CF
Probability of Clock Edge
within the Distribution
± 1σ
0.68268948
± 2σ
0.95449988
± 3σ
0.99730007
± 4σ
0.99993663
± 5σ
0.99999943
± 6σ
0.99999999
VCO Frequency [MHz]
200
250
300
350
400
450
480
160
140
120
100
80
60
40
20
0
FB=
÷32
FB=
÷16
FB=
÷8
FB=
÷4
Max. I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
t jit(
)[p
s]
RMS
VCO Frequency [MHz]
200
250
300
350
400
450
480
120
100
80
60
40
20
0
FB=
÷12
FB=
÷24
Max. I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
FB=
÷6
t jit(
)[p
s]
RMS
VCO Frequency [MHz]
200
250
300
350
400
450
480
140
120
100
80
60
40
20
0
FB=
÷20
FB=
÷10
FB=
÷40
Max. I/O Phase Jitter versus Frequency
Parameter: PLL Feedback Divider FB
t jit
(
)[p
s]
RMS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9772FAR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9773 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:3.3 V 1:12 LVCMOS PLL Clock Generator |
| MPC9773AE | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9773AER2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS/LVPE CL to LVCMOS PLL Clo RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9773FA | 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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