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參數(shù)資料
| 型號： | MPC974FA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 974 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 469K |
| 代理商： | MPC974FA |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC974/D
1
REV 3
Motorola, Inc. 2000
6/00
3.3V PLL Clock Driver
The MPC974 is a fully integrated PLL based clock generator and clock
distribution chip which operates from a 3.3V supply. The MPC974 is
ideally suited for high speed, timing critical designs which need a high
level of clock fanout. The device features 15 high drive LVCMOS outputs,
each output has the capability of driving a 50
parallel terminated
transmission line or two 50
series terminated transmission lines on the
incident edge.
Fully Integrated PLL
Two Reference Clock Inputs for Redundant Clock Applications
High Impedance Output Control
Logic Enable on the Outputs
3.3V VCC Supply
Output Frequency Configurable
LQFP Packaging
±100ps Typical Cycle–to–Cycle Jitter
The MPC974 features 3 independent frequency programmable banks
of outputs. The frequency programmability offers the capability of
establishing output frequency relationships of 1:1, 2:1, 3:1, 3:2 and 3:2:1.
In addition, the device features a separate feedback output which allows
for a wide variety of input/output frequency multiplication alternatives.
The VCO_Sel pin provides an extended VCO lock range for added
flexibility and general purpose usage.
The TCLK0 and TCLK1 inputs provide a method for dynamically
switching the PLL between two different clock sources. The PLL has been
optimized to provide small deviations in output pulse width and well
controlled, slow transition back to lock when the inputs are switched
between two references that are equal in frequency but out of phase with
each other. This feature makes the MPC974 a solution for fault tolerant
applications which require redundant clock sources.
For designs in which fault tolerance is critical, other products may provide more control over the clock switch functions. For
these features please refer to the MPC993 datasheet.
All of the control pins are LVTTL/LVCMOS level inputs. The Fsel pins control the VCO divide ratios that are applied to the
various output banks and the feedback output. The MR input will reset the internal flip flops and place the outputs in high
impedance when driven LOW. The OE pin will force all of the outputs except the feedback output LOW to allow for acquiring
phase lock prior to providing clocks to the rest of the system. Note that the OE pin is not synchronized to the internal clock. As a
result, the initial pulse after de–assertion of the OE pin may be distorted. The PLL_En pin allows the PLL to be bypassed for
board level functional test. When bypassed the signal on the selected TCLK will be routed around the PLL and will drive the
internal dividers directly.
The MPC974 is packaged in the 52–lead LQFP package to provide optimum electrical performance as well as minimize board
space requirements. The device is specified for 3.3V VCC.
MPC974
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
52–LEAD LQFP PACKAGE
CASE 848D-03
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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DATA SHEET
MPC974
IDT 3.3 V PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC974
1
3.3 V PLL Clock Driver
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| MPC9773AE | 9773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
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| MPC97H74FAR2 | 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC97H74FA | 97H SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MPC9893FAR2 | 9893 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9772 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V 1:12 LVCMOS PLL Clock Generator |
| MPC9772AE | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772AER2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9772FA | 功能描述:鎖相環(huán) - PLL 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9772FAR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-12 LVCMOS PLL Clock Generator, xta RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
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