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參數(shù)資料
| 型號(hào)： | MPC972FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 125 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 171K |
| 代理商： | MPC972FAR2 |
MPC972
MOTOROLA
TIMING SOLUTIONS
2
fselb1
fselb0
fsela1
fsela0
Qa3
VCCO
Qa2
GNDO
Qa1
VCCO
Qa0
GNDO
VCO_Sel
fselFB1
QSync
GNDO
Qc0
VCCO
Qc1
fselc0
fselc1
Qc2
VCCO
Qc3
GNDO
Inv_Clk
GNDO
Qb0
VCCO
Qb1
GNDO
Qb2
VCCO
Qb3
Ext_FB
GNDO
QFB
VCCI
fselFB0
GNDI
MR/OE
Frz_Clk
Frz_Data
fselFB2
PLL_EN
Ref_Sel
TClk_Sel
TClk0
TClk1
xtal1
xtal2
VCCA
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
1234
56789
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
26
MPC972
Figure 1. 52–Lead Pinout (Top View)
All inputs have internal pull–up resistors (appr. 50K) except for the xtal1 and xtal2 pins.
FUNCTION TABLE 1
fsela1
fsela0
Qa
fselb1
fselb0
Qb
fselc1
fselc0
Qc
0
1
0
1
0
1
÷4
÷6
÷8
÷12
0
1
0
1
0
1
÷4
÷6
÷8
÷10
0
1
0
1
0
1
÷2
÷4
÷6
÷8
FUNCTION TABLE 2
*fselFB2
fselFB1
fselFB0
QFB
0
1
0
1
0
1
÷4
÷6
÷8
÷10
1
0
1
0
1
0
1
÷8
÷12
÷16
÷20
*If the fselFB2 is 1, it may be necessary to apply a reset after power
up to ensure synchronization between QFB and the other inputs.
FUNCTION TABLE 3
Control Pin
Logic ‘0’
Logic ‘1’
VCO_Sel
VCO/2
VCO
Ref_Sel
TCLK
Xtal (PECL)
TCLK_Sel
TCLK0
TCLK1
PLL_En
Bypass PLL
Enable PLL
MR/OE
Master Reset/Output Hi–Z
Enable Outputs
Inv_Clk
Non–Inverted Qc2, Qc3
Inverted Qc2, Qc3
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