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參數(shù)資料
| 型號(hào)： | MPC972FA |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 125 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁(yè)數(shù)： | 13/13頁(yè) |
| 文件大?。?/td> | 631K |
| 代理商： | MPC972FA |
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MPC972
9
MOTOROLA
Using the On–Board Crystal Oscillator
The MPC972 features an on–board crystal oscillator to allow
for seed clock generation as well as final distribution. The
on–board oscillator is completely self contained so that the only
external component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs the user is advised
to mount the crystal as close to the MPC972 as possible to
avoid any board level parasitics. To facilitate co–location
surface mount crystals are recommended, but not required.
The oscillator circuit is a series resonant circuit as opposed
to the more common parallel resonant circuit, this eliminates
the need for large on–board capacitors. Because the design is
a series resonant design for the optimum frequency accuracy
a series resonant crystal should be used (see specification
table below). Unfortunately most of the shelf crystals are
characterized in a parallel resonant mode. However a parallel
resonant crystal is physically no different than a series resonant
crystal, a parallel resonant crystal is simply a crystal which has
been characterized in its parallel resonant mode. Therefore in
the majority of cases a parallel specified crystal can be used
with the MPC972 with just a minor frequency error due to the
actual series resonant frequency of the parallel resonant
specified crystal. Typically a parallel specified crystal used in a
series resonant mode will exhibit an oscillatory frequency a few
hundred ppm lower than the specified value. For most
processor implementations a few hundred ppm translates into
kHz inaccuracies, a level which does not represent a major
issue.
3. Crystal Recommendations
Parameter
Value
Crystal Cut
Fundamental AT Cut
Resonance
Series Resonance*
Frequency Tolerance
±75 ppm at 25°C
Frequency/Temperature Stability
±150 pm 0 to 70°C
Operating Range
0 to 70
°C
Shunt Capacitance
5–7 pF
Equivalent Series Resistance (ESR)
50 to 80
Max
Correlation Drive Level
100
W
Aging
5 ppm/Yr (First 3 Years)
* See accompanying text for series versus parallel resonant
discussion.
The MPC972 is a clock driver which was designed to
generate outputs with programmable frequency relationships
and not a synthesizer with a fixed input frequency. As a result
the crystal input frequency is a function of the desired output
frequency. For a design which utilizes the external feedback to
the PLL the selection of the crystal frequency is straight
forward; simply chose a crystal which is equal in frequency to
the fed back signal.
Recommended External Reset Timing
For MPC972 applications requiring synchronization of the
output clock to the input clock and if fselFB2 = 1, the assertion
of MR is recommended. The timing of asserting MR should be
as shown in 1. The power supply should be at or above the
minimum specified voltage and the reference clock input
(refclk) should be present a minimum of t1 prior to the reset
pulse being applied to the MR pin.
Figure 1. Assertion of MR
refclk
VDD Power
MR
VDD -5%
t1
t2
t1 > 10 msec
10 ns < t2 < 20 ns
Power Supply Filtering
The MPC972 is a mixed analog/digital product and exhibits
some sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to
random noise, especially if this noise is seen on the power
supply pins. The MPC972 provides separate power supplies for
the output buffers (VCCO) and the internal PLL (VCCA) of the
device. The purpose of this design technique is to try and isolate
the high switching noise digital outputs from the relatively
sensitive internal analog phase–locked loop. In a controlled
environment such as an evaluation board this level of isolation
is sufficient. However, in a digital system environment where it
is more difficult to minimize noise on the power supplies a
second level of isolation may be required. The simplest form of
isolation is a power supply filter on the VCCA pin for the
MPC972.
Figure 10. Power Supply Filter
VCCA
VCC
MPC972
0.01 F
22 F
0.01 F
3.3 V
RS=5-10
Figure 10 illustrates a typical power supply filter scheme. The
MPC972 is most susceptible to noise with spectral content in
the 1 KHz to 1 MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs to
be met in the final filter design is the DC voltage drop that will
be seen between the VCC supply and the VCCA pin of the
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MPC972
Low Voltage PLL Clock Driver
NETCOM
IDT Low Voltage PLL Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC972
9
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