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參數(shù)資料
| 型號(hào)： | MPC96877VKR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DRIVER 1:10 SDRAM 52-BGA |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR2，SDRAM |
| 輸入： | 時(shí)鐘 |
| 輸出： | SSTL-18 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 340MHz |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-BGA |
| 包裝： | 帶卷 (TR) |
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MPC96877
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
551
Table 3. Absolute Maximum Ratings Over Free-Air Operating Range1
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Parameter
Value
Supply voltage range, VDDQ or AVDD
–0.5 V to 2.5 V
Input voltage range, VI2, 3
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 2.5 V maximum.
–0.5 V to VDDQ + 0.5 V
Output voltage range, VO1, 2
–0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VDDQ)
±50 mA
Output clamp voltage, IOK (VO < 0 or VO > VDDQ)
±50 mA
Continuous output current, IO (VO = 0 to VDDQ)
±50 mA
Continuous current through each VDDQ or GND
±100 mA
Storage temperature range, TSTG
–65
°C to 150°C
Table 4. Recommended Operating Conditions
Rating
Parameter
Affected Pins
Min
Nom
Max
Unit
Output supply voltage
VDDQ
1.7
1.8
1.9
V
Supply voltage1
1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended
operating conditions and not timing parameters are guaranteed.
AVDD
VDDQ
Low-level input voltage2
2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 12. Time Delay between OE and Clock
Output for definition. For CK and CK the VIH and VIL limits are used to define the DC low and high levels for the logic detect state.
VIL
OE, OS, CK, CK
0.35 x VDDQ
V
High-level input voltage2
VIH
OE, OS, CK, CK
0.65 x VDDQ
High-level output current
IOH
–9
mA
Low-level output current
IOL
9
mA
Input differential-pair cross voltage
VIX
(VDDQ/2) –0.15
(VDDQ/2) +0.15
V
Input voltage level
VIN
–0.3
VDDQ +0.3
Input differential-pair voltage2
(see Figure 9. Half-Period Jitter)
VID
DC
0.3
VDDQ +0.4
AC
0.6
VDDQ +0.4
Operating free-air temperature
0
70
°C
MPC96877
1.8 V PLL 1:10 Differential SDRAM Clock Driver
NETCOM
IDT 1.8 V PLL 1:10 Differential SDRAM Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC96877
5
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