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參數(shù)資料
| 型號： | MPC9658ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 1:10 3.3V 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVPECL |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 250MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC9658 REVISION 6 JANUARY 8, 2013
5
2013 Integrated Device Technology, Inc.
MPC9658 Data Sheet
3.3V 1:10 LVCMOS PLL CLOCK GENERATOR
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input reference frequency
2 feedback(2)
PLL mode, external feedback
4 feedback(3)
Input reference frequency in PLL bypass mode(4)
2.
2 PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE =0.
3.
4 PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE =0.
4. In bypass mode, the MPC9658 divides the input reference clock.
100
50
0
250
125
250
MHz
PLL locked
fVCO
VCO lock frequency range(5)
5. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF =fVCO FB.
200
500
MHz
fMAX
Output Frequency
2 feedback(3)
4 feedback(4)
100
50
250
125
MHz
PLL locked
VPP
Peak-to-peak input voltage (PCLK)
500
1000
mV
LVPECL
VCMR(6)
6. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
Common Mode Range (PCLK)
1.2
VCC –0.9
V
LVPECL
tPW,MIN
Input Reference Pulse Width(7)
7. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF,MIN.
2.0
ns
t()
Propagation Delay (static phase offset)
PCLK to FB_IN
fREF = 100 MHz
any frequency
–70
–125
+80
+125
ps
PLL locked
tPD
Propagation Delay (PLL and divider bypass)
PCLK to Q0-9
1.0
4.0
ns
tsk(O)
Output-to-output Skew(8)
8. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation in PLL zero-delay mode.
120
ps
DC
Output Duty Cycle(9)
9. Output duty cycle is DC = (0.5 ± 400 ps
fOUT) 100%. For example, the DC range at fOUT = 100MHz is 46% < DC < 54%. T = output period.
(T
2)–400
T
2
(T
2)+400
ps
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
tPLZ, HZ
Output Disable Time
7.0
ns
tPZL, LZ
Output Enable Time
6.0
ns
tJIT(CC)
Cycle-to-cycle jitter
80
ps
tJIT(PER)
Period Jitter
80
ps
tJIT()
I/O Phase Jitter fVCO = 500 MHz and 2 feedback, RMS (1)(10)
fVCO = 500 MHz and 4 feedback, RMS (1)
10. Refer to APPLICATIONS INFORMATION for a jitter calculation for other confidence factors than 1
and a characteristic for other VCO
frequencies.
5.5
6.5
ps
BW
PLL closed loop bandwidth(11)
2 feedback(3)
4 feedback(5)
11. –3 dB point of PLL transfer characteristics.
6 – 20
2 – 8
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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