參數(shù)資料
型號(hào)： MPC961CFA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： PLASTIC, LQFP-32
文件頁數(shù)： 3/9頁
文件大?。?/td> 159K
代理商： MPC961CFA
MPC961C
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
485
Table 3. Absolute Maximum Ratings1
1.
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
–0.3
3.6
V
VIN
DC Input Voltage
–0.3
VCC + 0.3
V
VOUT
DC Output Voltage
–0.3
VCC + 0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TS
Storage Temperature
–40
125
°C
Table 4. DC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input LOW Voltage
–0.3
0.8
V
LVCMOS
VOH
Output HIGH Voltage
2.4
V
IOH = –20 mA
1
1.
The MPC961C is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up two 50 series terminated transmission lines.
VOL
Output LOW Voltage
0.55
V
IOL = 20 mA
ZOUT
Output Impedance
14
20
IIN
Input Current
±120
A
CIN
Input Capacitance
4.0
pF
CPD
Power Dissipation Capacitance
8.0
10
pF
Per Output
ICCA
Maximum PLL Supply Current
2.0
5.0
mA
VCCA Pin
ICC
Maximum Quiescent Supply Current
mA
All VCC Pins
VTT
Output Termination Voltage
VCC ÷ 2
V
Table 5. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to 85°C)
1
1.
AC characteristics apply for parallel output termination of 50
to V
TT
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
fMAX
Maximum Output Frequency
F_RANGE = 0
F_RANGE = 1
100
50
200
100
MHz
fREFDC
Reference Input Duty Cycle
25
75
%
tr, tf
TCLK Input Rise/Fall Time
3.0
ns
0.7 to 1.7 V
t()
Propagation Delay
CCLK to FB_IN
(static phase offset)
–80
120
ps
PLL locked
tsk(O)
Output-to-Output Skew2
2.
Refer to APPLICATIONS INFORMATION for part-to-part skew calculation.
90
150
ps
DCO
Output Duty Cycle
F_RANGE = 0
F_RANGE = 1
40
45
50
60
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.6 to 1.8 V
tPLZ,HZ
Output Disable Time
10
ns
tPZL,LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-Cycle Jitter
RMS (1
σ)3
3.
Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1
σ.
15
ps
tJIT(PER)
Period Jitter
RMS (1
σ)
7.0
10
ps
tJIT()
I/O Phase Jitter
RMS (1
σ)
15
ns
tlock
Maximum PLL Lock Time
10
ms
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