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參數資料
| 型號： | MPC9608FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數： | 8/12頁 |
| 文件大?。?/td> | 239K |
| 代理商： | MPC9608FAR2 |
MPC9608
TIMING SOLUTIONS
5
a.
AC characteristics apply for parallel output termination of 50
to V
TT.
b.
PLL mode requires PLL_EN = 0 to enable the PLL and zero-delay operation.
c.
In bypass mode, the MPC9608 divides the input reference clock.
d.
Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the minimum and maximum output frequency of bank B is divided by two.
e.
Calculation of reference duty cycle limits: DCREF, MIN =tPW, MIN * fREF *100% and DCREF, MAX = 100% – DCREF, MIN. For example, at
fREF = 100 MHz the input duty cycle range is 20% < DC < 80%.
f.
-3 dB point of PLL transfer characteristics.
TABLE 7. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40° to 85°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input reference frequency in PLL modeb
F_RANGE = 00
F_RANGE = 01
F_RANGE = 10
F_RANGE = 11
Input reference frequency in PLL bypass modec
100
50
25
12.5
0
200
100
50
25
200
MHz
fmax
Output Frequencyd
F_RANGE = 00
F_RANGE = 01
F_RANGE = 10
F_RANGE = 11
100
50
25
12.5
200
100
50
25
MHz
BSEL = 0
tPW, MIN
Reference Input Pulse Widthe
2.0
ns
tr, tf
CCLK Input Rise/Fall Time
1.0
ns
0.8 V to 2.0 V
t()
Propagation Delay (SPO) CCLK to FB_IN
fref = 100 MHz and above
fref = 12.5 MHz to 100 MHz
-175
-1.75% of tPER
+175
+1.75% of tPER
ps
PLL Locked
tSK(o)
Output-to-Output Skew
Within a bank
Bank-to-bank
All outputs, inluding QFB
80
100
150
ps
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 V to 2.4 V
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-cycle jitter
150
ps
BSEL = 0
tJIT(PER)
Period Jitter
150
ps
BSEL = 0
tJIT()
I/O Phase Jitter
RMS (1
σ)
125
ps
BSEL = 0
BW
PLL closed loop bandwidthf
F_RANGE = 00
F_RANGE = 01
F_RANGE = 10
F_RANGE = 11
7 – 15
2 – 7
1 – 3
0.5 – 1.3
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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