參數資料
型號： MPC953FAR2
廠商： MOTOROLA INC
元件分類： 時鐘及定時
英文描述： PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝： 7 X 7 MM, PLASTIC, LQFP-32
文件頁數： 3/5頁
文件大?。?/td> 106K
代理商： MPC953FAR2
5
MPC953
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
454
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
VIH
Input HIGH Voltage
LVCMOS Inputs
2.0
3.6
V
VIL
Input LOW Voltage
LVCMOS Inputs
0.8
V
VPP
Peak–to–Peak Input Voltage
PECL_CLK
300
1000
mV
VCMR
Common Mode Range
PECL_CLK
VCC–1.5
VCC–0.6
mV
Note 1.
VOH
Output HIGH Voltage
VCC–0.6
V
IOH = –20mA, Note 2.
VOL
Output LOW Voltage
0.6
V
IOL = 20mA, Note 2.
IIN
Input Current
±120
A
CIN
Input Capacitance
4
pF
Cpd
Power Dissipation Capacitance
25
pF
Per Output
ICC
Maximum Quiescent Supply Current
75
mA
All VCC Pins
ICCPLL
Maximum PLL Supply Current
15
20
mA
VCCA Pin Only
1. VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
the VCMR range and the input swing lies within the VPP specification.
2. The MPC953 outputs can drive series or parallel terminated (50
to VCC/2) 50 transmission lines on the incident edge (see Applications Info
section).
PLL INPUT REFERENCE CHARACTERISTICS (TA = 0 to 70°C)
Symbol
Characteristic
Min
Max
Unit
Condition
fref
Reference Input Frequency
25
110
MHz
Note 3.
frefDC
Reference Input Duty Cycle
25
75
%
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
AC CHARACTERISTICS (TA = 0°C to 70°C, VCC = 3.3V ±5%)
Symbol
Characteristic
Min
Typ
Max
Unit
Condition
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.8 to 2.0V, Note 6.
tpw
Output Duty Cycle
45
50
55
%
Note 6.
tsk(O)
Output–to–Output Skews
150
ps
Note 6.
fVCO
PLL VCO Lock Range
200
500
MHz
Note 6.
fmax
Maximum Output Frequency
PLL Mode
Bypass Mode
25
50
62.5
110
200
MHz
VCO_SEL = ’1’
VCO_SEL = ’0’
Note 6.
tpd(lock)
Input to FB_CLK Delay (with PLL Locked)
–75
125
ps
Note 4., 6.
tpd(bypass)
Input to Q Delay
3
7
ns
PLL Bypassed
N5 6
pd(yp
)
Part–to–Part Delay
1.5
ns
yp
Note 5., 6.
tPLZ,HZ
Output Disable Time
7
ns
Note 6.
tPZL
Output Enable Time
6
ns
Note 6.
tjitter
Cycle–to–Cycle Jitter
100
ps
Note 6.
tlock
Maximum PLL Lock Time
10
ms
4.
tpd(lock) is input reference frequency dependent. The tpd is specified at 50MHz ref, feedback B 8. The tpd does not include jitter.
5.
For a specified temperature and voltage, includes output skew.
6. Termination of 50
W to VCC/2.
相關PDF資料
PDF描述
MPC953FA 953 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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