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參數(shù)資料
| 型號(hào)： | MPC953FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 953 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數(shù)： | 4/5頁 |
| 文件大?。?/td> | 280K |
| 代理商： | MPC953FA |
5
MPC953
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
455
Power Supply Filtering
The MPC953 is a mixed analog/digital product and as such
it exhibits some sensitivities that would not necessarily be
seen on a fully digital product. Analog circuitry is naturally sus-
ceptible to random noise, especially if this noise is seen on the
power supply pins. The MPC953 provides separate power
supplies for the output buffers (VCCO) and the phase–locked
loop (VCCA) of the device. The purpose of this design tech-
nique is to try and isolate the high switching noise digital out-
puts from the relatively sensitive internal analog phase–locked
loop. In a controlled environment such as an evaluation board
this level of isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
VCCA pin for the MPC953.
Figure 3 illustrates a typical power supply filter scheme. The
MPC953 is most susceptible to noise with spectral content in
the 100KHz to 10MHz range. Therefore the filter should be
designed to target this range. The key parameter that needs to
be met in the final filter design is the DC voltage drop that will
be seen between the VCC supply and the VCCA pin of the
MPC953. From the data sheet the IVCCA current (the current
sourced through the VCCA pin) is typically 15mA (20mA maxi-
mum), assuming that a minimum of 3.0V must be maintained
on the VCCA pin very little DC voltage drop can be tolerated
when a 3.3V VCC supply is used. The resistor shown in
Figure 3 must have a resistance of 10–15
to meet the voltage
drop criteria. The RC filter pictured will provide a broadband
filter with approximately 100:1 attenuation for noise whose
spectral content is above 20KHz. As the noise frequency
crosses the series resonant point of an individual capacitor it’s
overall impedance begins to look inductive and thus increases
with increasing frequency. The parallel capacitor combination
shown ensures that a low impedance path to ground exists for
frequencies well above the bandwidth of the PLL. It is recom-
mended that the user start with an 8–10
resistor to avoid
potential VCC drop problems and only move to the higher value
resistors when a higher level of attenuation is shown to be
needed.
Figure 3. Power Supply Filter
VCCA
VCC
MPC953
0.01F
22F
0.01F
3.3V
RS=5-15
Although the MPC953 has several design features to mini-
mize the susceptibility to power supply noise (isolated power
and grounds and fully differential PLL) there still may be ap-
plications in which overall performance is being degraded due
to system power supply noise. The power supply filter
schemes discussed in this section should be adequate to elim-
inate power supply noise related problems in most designs.
Driving Transmission Lines
The MPC953 clock driver was designed to drive high speed
signals in a terminated transmission line environment. To pro-
vide the optimum flexibility to the user the output drivers were
designed to exhibit the lowest impedance possible. With an
output impedance of approximately 20
the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091 in the Timing Solutions data book
(DL207/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a point–to–
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique termi-
nates the signal at the end of the line with a 50
resistance to
VCC/2. This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by each
output of the MPC953 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 4 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fan-
out of the MPC953 clock driver is effectively doubled due to its
capability to drive multiple lines.
Figure 4. Single versus Dual Transmission Lines
14
IN
MPC953
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC953
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots of Figure 5 show the simulation results
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC953 output buffers is more than suf-
ficient to drive 50
transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output–to–output skew of the
MPC953. The output waveform in Figure 5 shows a step in the
waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
43
series resistor plus the output impedance does not match
the parallel combination of the line impedances. The voltage
wave launched down the two lines will equal:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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