參數(shù)資料
型號: MPC953
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Low Voltage PLL Clock Driver(低壓PLL時鐘驅(qū)動器)
中文描述: 低電壓PLL時鐘驅(qū)動器(低壓鎖相環(huán)時鐘驅(qū)動器)
文件頁數(shù): 1/8頁
文件大?。?/td> 104K
代理商: MPC953
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC953/D
1
REV 3
Motorola, Inc. 2000
06/00
The MPC953 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree designs. With output frequencies
of up to 110MHz and output skews of 150ps the MPC953 is ideal for the
most demanding clock tree designs. The devices employ a fully
differential PLL design to minimize cycle–to–cycle and phase jitter.
Fully Integrated PLL
Output Frequency up to 110MHz in PLL Mode
Outputs Disable in High Impedance
LQFP Packaging
100ps Cycle–to–Cycle Jitter
The MPC953 has a differential LVPECL reference input along with an
external feedback input. These features make the MPC953 ideal for use
as a zero delay, low skew fanout buffer. The device performance has
been tuned and optimized for zero delay performance. The MR/OE input
pin will reset the internal counters and tristate the output buffers when
driven “high”.
The MPC953 is fully 3.3V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50
transmission lines. For series terminated
50
lines, each of the MPC953 outputs can drive two traces giving the
device an effective fanout of 1:18. The device is packaged in a 7x7mm
32–lead LQFP package to provide the optimum combination of board
density and performance.
Figure 1. Logic Diagram
PECL_CLK
PECL_CLK
FB_CLK
Phase
Detector
LPF
VCO
200–500MHz
÷
4
VCO_SEL
BYPASS
QFB
Q0:6
Q7
7
÷
2
MR/OE
PLL_EN
0
1
0
1
0
1
(Int pull up)
(Int pull up)
(Int pull up)
(Int pull up)
(Int pull down)
(Int pull up)
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
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