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參數(shù)資料
| 型號(hào)： | MPC951FAR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 951 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 303K |
| 代理商： | MPC951FAR2 |
MPC951
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
164
Using the MPC951 as a Zero Delay Buffer
The external feedback of the MPC951 clock driver allows
for its use as a zero delay buffer. By using one of the outputs as
a feedback to the PLL the propagation delay through the de-
vice is eliminated. The PLL works to align the output edge with
the input reference edge thus producing a near zero delay. The
input reference frequency affects the static phase offset of the
PLL and thus the relative delay between the inputs and out-
puts.
When used as a zero delay buffer the MPC951 will likely be
in a nested clock tree application. For these applications the
MPC951 offers a LVPECL clock input as a PLL reference. This
allows the user to use LVPECL as the primary clock distribu-
tion device to take advantage of its far superior skew perfor-
mance. The MPC951 then can lock onto the LVPECL refer-
ence and translate with near zero delay to low skew LVCMOS
outputs. Clock trees implemented in this fashion will show sig-
nificantly tighter skews than trees developed from CMOS fan-
out buffers.
To minimize part–to–part skew the external feedback option
again should be used. The PLL in the MPC951 decouples the
delay of the device from the propagation delay variations of the
internal gates. From the specification table one sees a Tpd
variation of only
±200ps, thus for multiple devices under identi-
cal configurations the part–to–part skew will be around 1000ps
(350ps for Tpd variation plus 350ps output–to–output skew
plus 300ps for I/O jitter). By running the devices at the highest
possible input reference, this part–to– part skew can be mini-
mized. Higher input reference frequencies will minimize both
I/O jitter and tpd variations.
Table 1. Programmable Output Frequency Relationships
INPUTS
OUTPUTS
fsela
fselb
fselc
fseld
Qa
Qb
Qc
Qd
0
VCO/2
VCO/4
0
1
VCO/2
VCO/4
VCO/8
0
1
0
VCO/2
VCO/4
VCO/8
VCO/4
0
1
VCO/2
VCO/4
VCO/8
0
1
0
VCO/2
VCO/8
VCO/4
0
1
0
1
VCO/2
VCO/8
VCO/4
VCO/8
0
1
0
VCO/2
VCO/8
VCO/4
0
1
VCO/2
VCO/8
1
0
VCO/4
1
0
1
VCO/4
VCO/8
1
0
1
0
VCO/4
VCO/8
VCO/4
1
0
1
VCO/4
VCO/8
1
0
VCO/4
VCO/8
VCO/4
1
0
1
VCO/4
VCO/8
VCO/4
VCO/8
1
0
VCO/4
VCO/8
VCO/4
1
VCO/4
VCO/8
MPC951
`1'
`0'
Input Ref
75MHz
Ext_FB
1
MPC951
`0'
`1'
Input Ref
25MHz
Ext_FB
1
fsela
fselb
fselc
fseld
fsela
fselb
fselc
fseld
75MHz
Qa
75MHz
Qb
75MHz
Qc
1
2
75MHz
Qd
5
Figure 1. “Zero” Delay Buffer
Figure 2. “Zero” Delay Frequency Multiplier
1
100MHz
Qa
50MHz
Qb
50MHz
Qc
1
2
25MHz
Qd
5
Jitter Performance of the MPC951
With the clock rates of today’s digital systems continuing to
increase more emphasis is being placed on clock distribution
design and management. Among the issues being addressed
is system clock jitter and how that affects the overall system
timing budget. The MPC951 was designed to minimize clock
jitter by employing a differential bipolar PLL as well as incorpo-
rating numerous power and ground pins in the design. The
following few paragraphs will outline the jitter performance of
the MPC951, illustrate the measurement limitations and pro-
vide guidelines to minimize the jitter of the device.
The most commonly specified jitter parameter is cycle–to–
cycle jitter. Unfortunately with today’s high performance mea-
surement equipment there is no way to measure this parame-
ter for jitter performance in the class demonstrated by the
MPC951. As a result different methods are used which approx-
imate cycle–to–cycle jitter. The typical method of measuring
the jitter is to accumulate a large number of cycles, create a
histogram of the edge placements and record peak–to–peak
as well as standard deviations of the jitter. Care must be taken
that the measured edge is the edge immediately following the
trigger edge. If this is not the case the measurement inaccura-
2
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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