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參數(shù)資料
| 型號(hào)： | MPC949FAR2 |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 949 SERIES, LOW SKEW CLOCK DRIVER, 15 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | 10 X 10 MM, 0.65 MM PITCH, PLASTIC, LQFP-52 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大?。?/td> | 272K |
| 代理商： | MPC949FAR2 |
6
MPC949
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
620
Figure 1. Logic Diagram
Figure 2. 52–Lead Pinout (Top View)
NC
VCCb
Qb2
GNDb
Qb1
VCCb
Qb0
GNDb
GNDa
Qa1
VCCa
Qa0
GNDa
NC
VCCd
Qd4
GNDd
Qd3
VCCd
Qd2
GNDd
Qd1
VCCd
Qd0
GNDd
NC
GNDc
Qc0
VCCc
Qc1
GNDc
Qc2
VCCc
Qc3
GNDc
GNDd
Qd5
NC
TCLK_Sel
MR/OE
VCCI
TCLK0
TCLK1
PCLK
PCLK_Sel
Dsela
Dselb
Dselc
Dseld
GNDI
40
41
42
43
44
45
46
47
48
49
50
51
52
25
24
23
22
21
20
19
18
17
16
15
14
1234 56789 10 11 12 13
39 38 37 36 35 34 33 32 31 30 29 28 27
26
MPC949
TCLK1
Qa0:1
TCLK0
TCLK_Sel
2
R
÷2
÷1
Dsela
Qc0:3
4
Dselc
Qd0:5
6
Dseld
MR/OE
Qb0:2
3
Dselb
PCLK
PCLK_Sel
0
1
0
1
0
1
0
1
0
1
0
1
FUNCTION TABLE
Input
0
1
TCLK_Sel
PCLK_Sel
Dseln
MR/OE
TCLK0
TCLKn
÷1
Enabled
TCLK1
PCLK
÷2
Hi–Z
PIN DESCRIPTION
Pin Name
Function
TCLK_Sel
(Int Pulldown)
Select pin to choose TCKL0 or TCLK1
TCLK0:1
(Int Pullup)
LVCMOS/LVTTL clock inputs
PCLK
(Int Pulldown)
True PECL clock input
PCLK
(Int Pullup)
Complement PECL clock input
Dseln
(Int Pulldown)
1x or 1/2x input divide select pins
MR/OE
(Int Pulldown)
Internal reset and output tristate control pin
PCLK_Sel
(Int Pulldown)
Select Pin to choose TCLK or PCLK
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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