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參數(shù)資料
| 型號： | MPC9456FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9456 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 312K |
| 代理商： | MPC9456FA |
Advanced Clock Drivers Devices
Freescale Semiconductor
5
MPC9456
Table 7. AC Characteristics (VCC = VCCA = VCCB = VCCC = 3.3 V ± 5%, TA = –40 to + 85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
250(2)
2. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
MHz
fMAX
Maximum Output Frequency
÷1 output
÷2 output
0
250(2)
125
MHz
FSELx = 0
FSELx = 1
VPP
Peak-to-Peak Input Voltage
PCLK
500
1000
mV
LVPECL
VCMR(3)
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification.
Common Mode Range
PCLK
1.3
VCC–0.8
V
LVPECL
tP, REF
Reference Input Pulse Width
1.4
ns
tr, tf
PCLK Input Rise/Fall Time
1.0(4)
4. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
ns
0.8 to 2.0 V
tPLH
tPHL
Propagation Delay
CCLK to any Q
2.2
2.8
4.45
4.2
ns
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tsk(O)
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
200
350
ps
tsk(PP)
Device-to-Device Skew
2.25
ns
tSK(P)
DCQ
Output Pulse Skew(5)
Output Duty Cycle
÷1 output
÷2 output
5. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%.
47
45
50
200
53
55
ps
%
DCREF = 50%
DCREF = 25%–75%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4 V
Table 8. DC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40 to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input high voltage
1.7
VCC+0.3
V
LVCMOS
VIL
Input low voltage
–0.3
0.7
V
LVCMOS
VPP
Peak-to-peak input voltage
PCLK
250
mV
LVPECL
VCMR(1)
1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
Common Mode Range
PCLK
1.1
VCC–0.7
V
LVPECL
VOH
Output High Voltage
1.8
V
IOH = –15 mA(2)
2. The MPC9456 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per
output.
VOL
Output Low Voltage
0.6
V
IOL = 15 mA
ZOUT
Output impedance
17
–20(2)
IIN
Input current(3)
3. Input pull-up / pull-down resistors influence input current.
±200
AVIN = GND or VIN = VCC
ICCQ(4)
4. CCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Maximum Quiescent Supply Current
2.0
mA
All VCC Pins
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| MPC946 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 1:10 CMOS CLOCK DRIVER |
| MPC947 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 1:9 CLOCK DISTRIBUTION CHIP |
| MPC947FA | 制造商:Freescale Semiconductor 功能描述: |
| MPC948 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP |
| MPC948FA | 制造商:Motorola Inc 功能描述:TWELVE DISTRIBUTED-OUTPUT CLOCK DRIVER, 32 Pin, Plastic, QFP |
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