參數(shù)資料
型號(hào)： MPC9456AC
廠(chǎng)商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 10/13頁(yè)
文件大?。?/td> 0K
描述： IC CLK BUFF DVDR MUX 1:10 32LQFP
標(biāo)準(zhǔn)包裝： 250
類(lèi)型： 扇出緩沖器（分配），除法器，多路復(fù)用器，PLL
電路數(shù)： 1
比率 - 輸入:輸出： 1:10
差分 - 輸入:輸出： 是/無(wú)
輸入： LVCMOS，LVPECL
輸出： LVCMOS
頻率 - 最大： 250MHz
電源電壓： 2.375 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 托盤(pán)
ICS843N001BGI REVISION 4 DECEMBER 21, 2012
6
2012 Integrated Device Technology, Inc.
MPC9456 Data Sheet
2.5 V AND 3.3 V LVCMOS CLOCK FANOUT BUFFER
Table 9. AC Characteristics (VCC = VCCA = VCCB = VCCC = 2.5 V ± 5%, TA = –40 to +85C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
250(2)
2. The MPC9456 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
MHz
fMAX
Maximum Output Frequency
1 output
2 output
0
250(2)
125
MHz
FSELx = 0
FSELx = 1
VPP
Peak-to-Peak Input Voltage
PCLK
500
1000
mV
LVPECL
VCMR(3)
3. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification.
Common Mode Range
PCLK
1.1
VCC–0.7
V
LVPECL
tP, REF
Reference Input Pulse Width
1.4
ns
tr, tf
PCLK Input Rise/Fall Time
1.0(4)
4. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
ns
0.7 to 1.7 V
tPLH
tPHL
Propagation Delay
PCLK to any Q
2.6
5.6
5.5
ns
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tsk(O)
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
200
350
ps
tsk(PP)
Device-to-Device Skew
3.0
ns
tSK(P)
DCQ
Output Pulse Skew(5)
Output Duty Cycle
1 or 2 output
5. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) fOUT). For example at fOUT = 125 MHz the output duty cycle limit is 50% ± 2.5%.
45
50
200
55
ps
%DCREF = 50%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.6 to 1.8 V
Table 10. AC Characteristics (VCC = 3.3 V ± 5%, VCCA = VCCB = VCCC = 2.5 V ± 5% or 3.3 V ± 5%, TA = –40 to +85C)(1), (2)
1. AC characteristics apply for parallel output termination of 50
to VTT.
2. For all other AC specifications, refer to 2.5 V or 3.3 V tables according to the supply voltage of the output bank.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
tsk(O)
Output-to-Output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
250
350
ps
tsk(PP)
Device-to-Device Skew
2.5
ns
tPLH,HL
Propagation Delay
PCLK to any Q
See 3.3 V Table
tSK(P)
DCQ
Output Pulse Skew(3)
Output Duty Cycle
1 or 2 output
3. Output pulse skew tSK(P) is the absolute difference of the propagation delay times: | tPLH – tPHL |. Output duty cycle is frequency
dependent: DCQ = (0.5 ± tSK(P) fOUT).
45
50
250
55
ps
%DCREF = 50%
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