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參數(shù)資料
| 型號： | MPC9448FA |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 1:12 32-LQFP |
| 標準包裝： | 250 |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:12 |
| 差分 - 輸入:輸出： | 是/無 |
| 輸入： | LVCMOS，LVPECL |
| 輸出： | LVCMOS |
| 頻率 - 最大： | 350MHz |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2012 MPC9448FAIDT-ND |
MPC9448 REVISION 7 DECEMBER 21, 2012
6
2012 Integrated Device Technology, Inc.
MPC9448 Data Sheet
3.3V/2.5V LVCMOS 1:12 CLOCK FANOUT BUFFER
APPLICATION INFORMATION
Figure 3. Output Clock Stop (CLK_STOP)
Timing Diagram
Driving Transmission Lines
The MPC9448 clock driver was designed to drive high-
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of 17
(VCC =3.3 V),
the outputs can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note
AN1091. In most high performance clock networks, point-to-
point distribution of signals is the method of choice. In a point-
to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50
resistance to VCC2.
Figure 4. Single versus Dual Transmission Lines
This technique draws a fairly high level of DC current ,and
thus, only a single terminated line can be driven by each
output of the MPC9448 clock driver. For the series terminated
case, however, there is no DC current draw; thus, the outputs
can drive multiple series terminated lines. Figure 4 illustrates
an output driving a single series terminated line versus two
series terminated lines in parallel. When taken to its extreme,
the fanout of the MPC9448 clock driver is effectively doubled
due to its capability to drive multiple lines at VCC = 3.3 V.
Figure 5. Single versus Dual Line
Termination Waveforms
The waveform plots in Figure 5 show the simulation
results of an output driving a single line versus two lines. In
both cases, the drive capability of the MPC9448 output buffer
is more than sufficient to drive 50
transmission lines on the
incident edge. Note from the delay measurements in the
simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output-to-output skew of the MPC9448. The output waveform
in Figure 5 shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 33
series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the
two lines will equal:
VL =VS (Z0 (RS+R0 +Z0))
Z0 = 50 || 50
RS = 33 || 33
R0 = 17
VL = 3.0 (25 (16.5+17+25)
= 1.28 V
At the load end, the voltage will double, due to the near
unity reflection coefficient, to 2.5 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
CCLK or
PCLK
CLK_STOP
Q0 to Q11
17
IN
MPC9448
Output
Buffer
RS = 33
ZO = 50
OutA
17
IN
MPC9448
Output
BufferR
RS = 33
ZO = 50
OutB0
RS = 33
ZO = 50
OutB1
Time (ns)
Vo
ltag
e(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
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| MPC9448FAR2 | 功能描述:IC CLOCK BUFFER MUX 2:12 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:- 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| MPC9449 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5 V 1:15 PECL/LVCMOS |
| MPC9449AC | 功能描述:IC CLK BUFF DVDR MUX 3:15 52LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:- 標準包裝:1 系列:HiPerClockS™ 類型:扇出緩沖器（分配），多路復(fù)用器 電路數(shù):1 比率 - 輸入:輸出:2:18 差分 - 輸入:輸出:是/無 輸入:CML，LVCMOS，LVPECL，LVTTL，SSTL 輸出:LVCMOS，LVTTL 頻率 - 最大:250MHz 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:- 其它名稱:800-1923-6 |
| MPC9449AE | 功能描述:時鐘緩沖器 FSL 1-15 LVPECL/LVCM OS to LVCMOS Fanout RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| MPC9449AER2 | 功能描述:時鐘驅(qū)動器及分配 FSL 1-15 LVPECL/LVCM OS to LVCMOS Fanout RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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