參數(shù)資料
型號: MPC9446FA
廠商: MOTOROLA INC
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封裝: 7 X 7 MM, PLASTIC, LQFP-32
文件頁數(shù): 5/7頁
文件大小: 122K
代理商: MPC9446FA
6
MPC9446
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
571
Table 8: DC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)
Sym-
bol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
1.7
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
-0.3
0.7
V
LVCMOS
VOH
Output High Voltage
1.8
V
IOH=-15 mAa
VOL
Output Low Voltage
0.6
V
IOL= 15 mA
ZOUT
Output Impedance
17 - 20b
W
IIN
Input Currentb
±200
A
VIN=GND or VIN=VCC
ICCQc
Maximum Quiescent Supply Current
2.0
mA
All VCC Pins
a. The MPC9446 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmis-
sion line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output.
b. Input pull-up / pull-down resistors influence input current.
c. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 9: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
250c
MHz
fMAX
Maximum Output Frequency
÷1 output
÷2 output
0
250b
125
MHz
FSELx=0
FSELx=1
tP, REF
Reference Input Pulse Width
1.4
ns
tr, tf
CCLK Input Rise/Fall Time
1.0d
ns
0.7 to 1.7V
tPLH
tPHL
Propagation delay
CCLK0,1 to any Q
2.6
5.6
5.5
ns
tPLZ, HZ
Output Disable Time
10
ns
tPZL, LZ
Output Enable Time
10
ns
tsk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
200
350
ps
tsk(PP)
Device-to-device Skew
3.0
ns
tSK(P)
DCQ
Output pulse skewe
Output Duty Cycle
÷1 or ÷2 output
45
50
200
55
ps
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.6 to 1.8V
a. AC characteristics apply for parallel output termination of 50
to VTT.
b. AC specifications are design targets, final specification is pending device characterization.
c. The MPC9446 is functional up to an input and output clock frequency of 350 MHz and is characterized up to 250 MHz.
d. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input
pulse width, output duty cycle and maximum frequency specifications.
e. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 10: AC CHARACTERISTICS (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%,
TA = –40°C to +85°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
tsk(O)
Output-to-output Skew
Within one bank
Any output bank, same output divider
Any output, Any output divider
150
250
350
ps
tsk(PP)
Device-to-device Skew
2.5
ns
tPLH,HL
Propagation delay
CCLK0,1 to any Q
See 3.3V table
tSK(P)
DCQ
Output pulse skewc
Output Duty Cycle
÷1 or ÷2 output
45
50
250
55
ps
%
DCREF = 50%
a. AC characteristics apply for parallel output termination of 50
to VTT.
b. For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
c. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
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