參數(shù)資料
型號: MPC9443FAR2
廠商: MOTOROLA INC
元件分類: 時鐘及定時
英文描述: LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝: 7 X 7 MM, PLASTIC, LQFP-48
文件頁數(shù): 10/16頁
文件大小: 205K
代理商: MPC9443FAR2
MPC9443
TIMING SOLUTIONS
3
MOTOROLA
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK
Input
LVCMOS
LVCMOS clock inputs
PCLK0, PCLK0
Input
LVCMOS
LVPECL differential clock input
PCLK1, PCLK1
Input
LVCMOS
LVPECL differential clock input
FSELA, FSELB, FSELC, FSELD
Input
LVCMOS
Output bank divide select input
CCLK_SEL
Input
LVCMOS
LVCMOS/LVPECL clock input select
PCLK_SEL
Input
LVCMOS
PCLK0/PCLK1 clock input select
OE0, OE1
Input
LVCMOS
Output tristate control
CLK_STOP
Input
LVCMOS
Synchronous output enable/disable (clock stop) control
GND
Supply
Negative voltage supply
VCCA, VCCB, VCCC, VCCD
Supply
Positive voltage supply output bank (VCC)
VCC
Supply
Positive voltage supply core (VCC)
QA0 to QA4
Output
LVCMOS
Bank A outputs
QB0 to QB2
Output
LVCMOS
Bank B outputs
QC0 to QC2
Output
LVCMOS
Bank C outputs
QD0 to QD4
Output
LVCMOS
Bank D outputs
Table 2. Supported Single and Dual Supply Configurations
Supply Voltage
Configuration
VCC
1
1.
VCC is the positive power supply of the device core and input circuitry. VCC voltage defines the input threshold and levels.
VCCA
2
2.
VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels.
VCCB
3
3.
VCCB is the positive power supply of the bank B outputs. VCCB voltage defines bank B output levels.
VCCC
4
4.
VCCC is the positive power supply of the bank C outputs. VCCC voltage defines bank C output levels.
VCCD
5
5.
VCCD is the positive power supply of the bank D outputs. VCCD voltage defines bank D output levels.
GND
3.3 V Supply
3.3 V
0 V
Mixed Mode Supply
3.3 V
3.3 V or 2.5 V
0 V
2.5 V Supply
2.5 V
0 V
Table 3. Function Table (Controls)
Control
Default
0
1
CCLK_SEL
0
PCLK or PCLK1 active (LVPECL clock mode)
CCLK active (LVCMOS clock mode)
PCLK_SEL
0
PCLK0 active, PCLK1 inactive
PCLK1 active, PCLK0 inactive
FSELA
0
fQA0:4 = fREF
fQA0:4 = fREF ÷ 2
FSELB
0
fQB0:2 = fREF
fQB0:2 = fREF ÷ 2
FSELC
0
fQC0:2 = fREF
fQC0:2 = fREF ÷ 2
FSELD
0
fQD0:4 = fREF
fQD0:4 = fREF ÷ 2
CLK_STOP
0
Normal operation
Outputs are synchronously disabled (stopped) in logic
low state
OE0, OE1
00
Asynchronous output enable control. See Table 4. Output High-Impedance Control (OEN)
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