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參數(shù)資料
| 型號(hào)： | MPC941FAR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 941 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, LQFP-48 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 326K |
| 代理商： | MPC941FAR2 |
6
MPC941
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
543
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC941 clock driver was designed to drive high speed
signals in a terminated transmission line environment. To pro-
vide the optimum flexibility to the user the output drivers were
designed to exhibit the lowest impedance possible. With an
output impedance of less than 20
the drivers can drive either
parallel or series terminated transmission lines. For more infor-
mation on transmission lines the reader is referred to applica-
tion note AN1091 in the Timing Solutions data book
(DL207/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a point–to–
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique termi-
nates the signal at the end of the line with a 50
resistance to
VCC/2. This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by each
output of the MPC941 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 1 “Single ver-
sus Dual Transmission Lines” illustrates an output driving a
single series terminated line vs two series terminated lines in
parallel. When taken to its extreme the fanout of the MPC941
clock driver is effectively doubled due to its capability to drive
multiple lines.
Figure 1. Single versus Dual Transmission Lines
14
IN
MPC941
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC941
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots of Figure 2 “Single versus Dual Wave-
forms” show the simulation results of an output driving a single
line vs two lines. In both cases the drive capability of the
MPC941 output buffer is more than sufficient to drive 50
transmission lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43ps exists
between the two differently loaded outputs. This suggests that
the dual line driving need not be used exclusively to maintain
the tight output–to–output skew of the MPC941. The output
waveform in Figure 2 shows a step in the waveform, this step is
caused by the impedance mismatch seen looking into the driv-
er. The parallel combination of the 36
series resistor plus the
output impedance does not match the parallel combination of
the line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50
|| 50
Rs = 36
|| 36
Ro = 14
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.5V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
Figure 2. Single versus Dual Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 3 “Optimized Dual Line Termination” should be used.
In this case the series terminating resistors are reduced such
that when the parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
Figure 3. Optimized Dual Line Termination
14
MPC941
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 k 22 = 50 k 50
25
= 25
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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