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參數(shù)資料
| 型號(hào)： | MPC941AER2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 941 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48 |
| 封裝： | 7 X 7 MM, LQFP-48 |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 326K |
| 代理商： | MPC941AER2 |
6
MPC941
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
542
Table 5: DC CHARACTERISTICS (VCC = 2.5V
± 5%, T
A = –40 to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input high voltage
LVCMOS_CLK
1.7
VCC + 0.3
V
LVCMOS
VIL
Input low voltage
LVCMOS_CLK
-0.3
0.7
V
LVCMOS
IIN
Input current
±120a
A
VPP
Peak-to-peak input voltage
PECL_CLK,
PECL_CLK
500
mV
LVPECL
VCMR
Common Mode Range
PECL_CLK,
PECL_CLK
1.1
VCC-0.7
V
LVPECL
VOH
Output High Voltage
1.8
V
IOH=-15 mAb
VOL
Output Low Voltage
0.6
V
IOL= 15 mAb
IOZ
Output tristate leakage current
100
A
ZOUT
Output impedance
18 – 20
W
CPD
Power Dissipation Capacitance
7–8
10
pF
Per Output
CIN
Input capacitance
4.0
pF
ICCQ
Maximum Quiescent Supply Current
5
mA
All VCC Pins
VTT
Output termination voltage
VCC÷2
V
a. Input pull-up / pull-down resistors influence input current.
b. The MPC941 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
Table 6: AC CHARACTERISTICS (VCC = 2.5V
± 5%, T
A = –40 to +85°C)
a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fMAX
Maximum Output Frequency
0
250b
MHz
tr, tf
LVCMOS_CLK Input Rise/Fall Time
1.0c
ns
0.7 to 1.7V
tPLH
tPHL
Propagation delay
PECL_CLK to any Q
LVCMOS_CLK to any Q
1.3
1.0
2.1
1.8
2.9
2.6
ns
tPLZ, HZ
Output Disable Time
ns
tPZL, LZ
Output Enable Time
ns
tsk(O)
Output-to-output Skew PECL_CLK to any Q
LVCMOS_CLK to any Q
125
250
ps
tsk(PP)
Device-to-device Skew PECL_CLK to any Q
LVCMOS_CLK to any Q
1200
ps
For a given TA
and VCC, any Q
tsk(PP)
Device-to-device Skew PECL_CLK to any Q
LVCMOS_CLK to any Q
1600
ps
For any TA, VCC
and Q
DCQ
Output Duty Cycle
PECL_CLK to any Q
LVCMOS_CLK to any Q
45
50
60
55
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
0.2
1.0
ns
0.6 to 1.6V
a. AC characteristics apply for parallel output termination of 50
to VTT.
b. AC characteristics are guaranteed up to fmax. Please refer to the applications section for information on power consumption versus operating
frequency and thermal management.
c. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application, signal
transition times smaller than 3 ns can be applied to the MPC941.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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