參數(shù)資料
型號: MPC941AE
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 941 SERIES, LOW SKEW CLOCK DRIVER, 27 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48
封裝: 7 X 7 MM, PLASTIC, LEAD FREE, LQFP-48
文件頁數(shù): 8/12頁
文件大小: 690K
代理商: MPC941AE
IDT / ICS CLOCK DISTRIBUTION CHIP
5
MPC941 REV. 8 APRIL 29, 2008
MPC941
LOW VOLTAGE, 1:27 CLOCK DISTRIBUTION CHIP
Table 6. AC Characteristics (VCC = 2.5 V ± 5%, TA = –40 to +85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fMAX
Maximum Output Frequency
0
250(2)
2. AC characteristics are guaranteed up to fMAX. Please refer to the applications section for information on power consumption versus operating
frequency and thermal management.
MHz
tr, tf
LVCMOS_CLK Input Rise/Fall Time
1.0(3)
3. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application,
signal transition times smaller than 3 ns can be applied to the MPC941.
ns
0.7 to 1.7 V
tPLH
tPHL
Propagation Delay
PECL_CLK to any Q
LVCMOS_CLK to any Q
1.3
1.0
2.1
1.8
2.9
2.6
ns
tPLZ, HZ
Output Disable Time
ns
tPZL, LZ
Output Enable Time
ns
tsk(O)
Output-to-Output Skew
PECL_CLK to any Q
LVCMOS_CLK to any Q
125
250
ps
tsk(PP)
Device-to-Device Skew
PECL_CLK to any Q
LVCMOS_CLK to any Q
1200
ps
For a given TA and
VCC, any Q
tsk(PP)
Device-to-Device Skew
PECL_CLK to any Q
LVCMOS_CLK to any Q
1600
ps
For any TA, VCC
and Q
DCQ
Output Duty Cycle
PECL_CLK to any Q
LVCMOS_CLK to any Q
45
50
60
55
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
0.2
1.0
ns
0.6 to 1.6 V
相關(guān)PDF資料
PDF描述
MPC942CFA LOW SKEW CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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MPC9446FA LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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MPC9448ACR2 9448 SERIES, LOW SKEW CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
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