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參數(shù)資料
| 型號： | MPC9351AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DRIVER LV 32-LQFP |
| 標準包裝： | 250 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，LVPECL |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:9 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應商設備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
| 其它名稱： | 800-2256 MPC9351ACIDT-ND |
MPC9351 REVISION 6 JANUARY 31, 2013
7
2013 Integrated Device Technology, Inc.
MPC9351 Data Sheet
LOW VOLTAGE PLL CLOCK DRIVER
APPLICATIONS INFORMATION
Programming the MPC9351
The MPC9351 clock driver outputs can be configured into
several divider modes; in addition, the external feedback of
the device allows for flexibility in establishing various input to
output frequency relationships. The output divider of the four
output groups allows the user to configure the outputs into
1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even
dividers ensures that the output duty cycle is always 50%.
Table 9 illustrates the various output configurations. The
table describes the outputs using the input clock frequency
CLK as a reference.
The output division settings establish the output
relationship. In addition, it must be ensured that the VCO will
be stable given the frequency of the outputs desired. The
feedback frequency should be used to situate the VCO into a
frequency range in which the PLL will be stable. The design
of the PLL supports output frequencies from 25MHz to
200MHz, while the VCO frequency range is specified from
200MHz to 400MHz and should not be exceeded for stable
operation.
Using the MPC9351 in Zero-Delay Applications
Nested clock trees are typical applications for the
MPC9351. For these applications, the MPC9351 offers a
differential LVPECL clock input pair as a PLL reference. This
allows for the use of differential LVPECL primary clock
distribution devices such as the Freescale MC100EP111 or
MC10EP222, taking advantage of its superior low-skew
performance. Clock trees using LVPECL for clock
distribution, and the MPC9351 as LVCMOS PLL fanout buffer
with zero insertion delay, will show significantly lower clock
skew than clock distributions developed from CMOS fanout
buffers.
The external feedback option of the MPC9351 PLL allows
for its use as a zero-delay buffer. The PLL aligns the feedback
clock output edge with the clock input reference edge and
virtually eliminates the propagation delay through the device.
The remaining insertion delay (skew error) of the
MPC9351 in zero-delay applications is measured between
the reference clock input and any output. This effective delay
consists of the static phase offset (SPO or t()), I/O jitter
(tJIT(), phase or long-term jitter), feedback path delay and
the output-to-output skew (tSK(O) relative to the feedback
output.
Figure 3. MPC9351 Zero-Delay Configuration
(Feedback of QD4)
Table 9. Output Frequency Relationship(1) for an Example Configuration
1. Output frequency relationship with respect to input reference frequency CLK. QC1 is connected to EXT_FB. More frequency ratios are
available by the connection of QA to the feedback input (EXT_FB).
Inputs
Outputs
FSELA
FSELB
FSELC
FSELD
QA
QB
QC
QD
0
2 * CLK
CLK
0
1
2 * CLK
CLK
2
0
1
0
4 * CLK
2 * CLK
CLK
2* CLK
0
1
4 * CLK
2 * CLK
CLK
0
1
0
2 * CLK
CLK
2
CLK
0
1
0
1
2 * CLK
CLK
2
CLK
2
0
1
0
4 * CLK
CLK
2 * CLK
0
1
4 * CLK
CLK
1
0
CLK
1
0
1
CLK
2
1
0
1
0
2 * CLK
CLK
2 * CLK
1
0
1
2 * CLK
CLK
1
0
CLK
2
CLK
1
0
1
CLK
2
CLK
2
1
0
2 * CLK
CLK
2 * CLK
1
2 * CLK
CLK
MPC9351
TCLK
QA
fref = 100 MHz
REF_SEL
PLL_EN
FSELA
FSELB
FSELC
FSELD
Ext_FB
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
2 x 100 MHz
4 x 100 MHz
100 MHz (Feedback)
1
0
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9351ACR2 | 功能描述:時鐘驅動器及分配 FSL1-9 LVCMOS/LVPECL LVCMOS PLL Clk Gen RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC9351D | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low Voltage PLL Clock Driver |
| MPC9351FA | 功能描述:時鐘驅動器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC9351FAR2 | 功能描述:IC PLL CLOCK DRIVER LV 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應商設備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| MPC9352 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:11 LVCMOS ZERO DELAY CLOCK GENERATOR |
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