參數(shù)資料
型號(hào): MPC9330ACR2
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 11/13頁(yè)
文件大?。?/td> 0K
描述: IC PLL CLOCK GENERATOR 32-LQFP
標(biāo)準(zhǔn)包裝: 2,000
類型: PLL 時(shí)鐘發(fā)生器
PLL: 帶旁路
輸入: LVCMOS,晶體
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 3:6
差分 - 輸入:輸出: 無(wú)/無(wú)
頻率 - 最大: 120MHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 32-LQFP
供應(yīng)商設(shè)備封裝: 32-TQFP(7x7)
包裝: 帶卷 (TR)
MPC9330 REVISION 8 DECEMBER 19, 2012
7
2012 Integrated Device Technology, Inc.
MPC9330 Data Sheet
3.3V, 1:6, LVCMOS PLL CLOCK GENERATOR
Table 8. MPC9330 Example Configurations (Internal Feedback: FB_SEL = 0)
fref(1) [MHz]
1. fref is the input clock reference frequency (CCLK or XTAL).
PWR_DN
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
12.5–30.0
0
fref
4
(50-120 MHz) fref
4
(50-120 MHz) fref
2
(25-60 MHz)
0
1
fref
4
(50-120 MHz) fref
4
(50-120 MHz) fref
4 3
(16.6-40 MHz)
0
1
0
fref
4
(50-120 MHz) fref
2
(25-60 MHz) fref
2
(25-60 MHz)
0
1
fref
4
(50-120 MHz) fref
2
(25-60 MHz) fref
4 3
(16.6-40 MHz)
0
1
0
fref
2
(25-60 MHz) fref
4
(50-120 MHz) fref
2
(25-60 MHz)
0
1
0
1
fref
2
(25-60 MHz) fref
4
(50-120 MHz) fref
4 3
(16.6-40 MHz)
0
1
0
fref
2
(25-60 MHz) fref
2
(25-60 MHz) fref
2
(25-60 MHz)
0
1
fref
2
(25-60 MHz) fref
2
(25-60 MHz) fref
4 3
(16.6-40 MHz)
1
0
fref
2
(25-60 MHz) fref
2
(25-60 MHz) fref
(12.5-30 MHz)
1
0
1
fref
2
(25-60 MHz) fref
2
(25-60 MHz) fref
2 3
(8.33-20 MHz)
1
0
1
0
fref
2
(25-60 MHz) fref
(12.5-30 MHz) fref
(12.5-30 MHz)
1
0
1
fref
2
(25-60 MHz) fref
(12.5-30 MHz) fref
2 3
(8.33-20 MHz)
1
0
fref
(12.5-30 MHz) fref
2
(25-60 MHz) fref
(12.5-30 MHz)
1
0
1
fref
(12.5-30 MHz) fref
2
(25-60 MHz) fref
2 3
(8.33-20 MHz)
1
0
fref
(12.5-30 MHz) fref
(12.5-30 MHz)
1
fref
(12.5-30 MHz) fref
2 3
(8.33-20 MHz)
Table 9. MPC9330 Example Configurations (External Feedback and PWR_DN = 0)
PLL
Feedback
fref(1)
[MHz]
1. fref is the input clock reference frequency (CCLK or XTAL).
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
VCO
4(2)
2. QAx connected to FB_IN and FSELA=0, PWR_DN=0.
50–120
0
fref
(50-120 MHz) fref
2
(25-60 MHz)
0
1
fref
(50-120 MHz) fref
3
(16.6-40 MHz)
0
1
0
fref
(50-120 MHz) fref
2
(25-60 MHz) fref
2
(25-60 MHz)
0
1
fref
(50-120 MHz) fref
2
(25-60 MHz) fref
3
(16.6-40 MHz)
VCO
8(3)
3. QAx connected to FB_IN and FSELA=1, PWR_DN=0.
25–60
1
0
fref
(25-60 MHz) fref
2
(50-120 MHz) fref
(25-60 MHz)
1
0
1
fref
(25-60 MHz) fref
2
(50-120 MHz) fref 2
3
(16.6-40 MHz)
1
0
fref
(25-60 MHz) fref
(25-60 MHz)
1
fref
(25-60 MHz) fref
(25-60 MHz) fref 2
3
(16.6-40 MHz)
VCO
12(4)
4. QCx connected to FB_IN and FSELC=1, PWR_DN=0.
16.67–40
0
1
fref
3
(50-120 MHz) fref
3
(50-120 MHz) fref
(16.6-40 MHz)
011
fref
3
(50-120 MHz) fref
3 2
(25-60 MHz) fref
(16.6-40 MHz)
101
fref
3 2
(25-60 MHz) fref
3
(50-120 MHz) fref
(16.6-40 MHz)
111
fref
3 2
(25-60 MHz) fref
3 2
(25-60 MHz) fref
(16.6-40 MHz)
Table 10. MPC9330 Example Configurations (External Feedback and PWR_DN = 1)
PLL
Feedback
fref(1)
[MHz]
FSELA
FSELB
FSELC
QA[0:1]:fref ratio
QB[0:1]:fref ratio
QC[0:1]:fref ratio
VCO
16(2)
12.5–30
1
0
fref
(12.5-30 MHz) fref 2
(25-60 MHz) fref
(12.5-30 MHz)
1
0
1
fref
(12.5-30 MHz) fref 2
(25-60 MHz) fref 2
3 (8.33-20 MHz)
1
0
fref
(12.5-30 MHz) fref
(12.5-30 MHz)
1
fref
(12.5-30 MHz) fref
(12.5-30 MHz) fref 2
3 (8.33-20 MHz)
VCO
24(3)
8.33–20
0
1
fref 3
(25-60 MHz) fref 3
(25-60 MHz) fref
(8.33-20 MHz)
0
1
fref 3
(25-60 MHz) fref 3
2 (12.5-30 MHz) fref
(8.33-20 MHz)
10
1
fref 3
2 (12.5-30 MHz) fref 3
(25-60 MHz) fref
(8.33-20 MHz)
11
1
fref 3
2 (12.5-30 MHz) fref 3 2 (12.5-30 MHz) fref
(8.33-20 MHz)
1. fref is the input clock reference frequency (CCLK or XTAL).
2. QAx connected to FB_IN and FSELA=1, PWR_DN=1.
3. QCx connected to FB_IN and FSELC=1, PWR_DN=1.
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