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參數(shù)資料
| 型號： | MPC931FA |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LVCMOS/LVTTL SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, TQFP-32 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 141K |
| 代理商： | MPC931FA |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
49
Low Voltage PLL Clock Driver
The MPC930/931 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock applications. With output frequencies
of up to 150MHz and output skews of 300ps the MPC930/931 is ideal for
the most demanding clock distribution designs. The device employs a
fully differential PLL design to minimize cycle to cycle and long term jitter.
This parameter is of significant importance when the clock driver is pro-
viding the reference clock for PLL’s on board todays microprocessors and
ASiC’s. The device offers 6 low skew outputs, and a choice between
internal or external feedback. The feedback option adds to the flexibility of
the device, providing numerous input to output frequency relationships.
On–Board Crystal Oscillator (MPC930)
Differential LVPECL Reference Input (MPC931)
Fully Integrated PLL
Output Shut Down Mode
Output Frequency up to 150MHz
Compatible with PowerPC and Intel Microprocessors
32–Lead TQFP Packaging
Power Down Mode
±100ps Typical Cycle–to–Cycle Jitter
The MPC930 and MPC931 are very similar in basic functionality, but
there are some minor differences. The MPC931 has been optimized for
use as a zero delay buffer. In addition to tighter specification limits on the
phase offset of the device, a higher speed VCO has been used on the
MPC931. The MPC930, on the other hand, is more optimized for use as a
clock generator. When choosing between the 930 and 931, pay special
attention to the differences in the AC parameters of each device.
The MPC930/931 offers two power saving features for power conscious portable or “green” designs. The power down pin will
seemlessly reduce all of the clock rates by one half so that the system will run at half the potential clock rate to extend battery life.
The POWER_DN pin is synchronized internally to the slowest output clock rate. This allows the transition in and out of the
power–down mode to be output glitch free. In addition, the shut down control pins will turn off various combinations of clock
outputs while leaving a subset active to allow for total processor shut down while maintaining system monitors to “wake up” the
system when signaled. During shut down, the PLL will remain locked, if internal feedback is used, so that wake up time will be
minimized. The shut down and power down pins can be combined for the ultimate in power savings. The Shut_Dn pins are
synchronized to the clock internal to the chip to eliminate the possibility of generating runt pulses.
The MPC930/931 devices offer a great deal of flexibility in what is used as the PLL reference. The MPC930 offers an inte-
grated crystal oscillator that allows for an inexpensive crystal to be used as the frequency reference. For more information on the
crystal oscillator please refer to the applications section of this data sheet. In those applications where the 930/931 will be used to
regenerate clocks from an existing source or as a zero delay buffer, alternative reference clock inputs are provided. Both devices
offer an LVCMOS input that can be used as the PLL reference. In addition the MPC931 replaces the crystal oscillator inputs with
a differential PECL reference clock input that allows the device to be used in mixed technology clock distribution trees.
An internal feedback divide by 8 of the VCO frequency is compared with the input reference provided by the on–board crystal
oscillator when the internal feedback is selected. The on–board crystal oscillator requires no external components other than a
series resonant crystal (see Applications Information section for more on crystals). The internal VCO is running at 8x the input
reference clock. The outputs can be configured to run at 4x, 2x, 1.25x or 0.66x the input reference frequency. If the external
feedback is selected, one of the MPC931’s outputs must be connected to the Ext_FB pin. Using the external feedback, numerous
input/output frequency relationships can be developed.
The MPC930/931 is fully 3.3V compatible and requires no external loop filter components. All control inputs accept LVCMOS
or LVTTL compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50
transmission
lines. For series terminated applications, each output can drive two 50
transmission lines, effectively increasing the fanout to
1:12. The device is packaged in a 32–lead TQFP package to provide the optimum combination of board density and cost.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
2
MPC930
MPC931
LOW VOLTAGE
PLL CLOCK DRIVER
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
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相關(guān)代理商/技術(shù)參數(shù) |
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| MPC932 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9330 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
| MPC9330AC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 FSL 1-6 LVCMOS PLL Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9330ACR2 | 功能描述:IC PLL CLOCK GENERATOR 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC9330FA | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3V 200MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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