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參數(shù)資料
| 型號： | MPC92469FA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 907K |
| 代理商： | MPC92469FA |
IDT / ICS PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
5
MPC92469REV 4 JANUARY 23, 2007
MPC92469
400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal Interface Frequency Range
12
20
MHz
fVCO
VCO Frequency Range(2)
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL x M ÷ 8.
400
800
MHz
fMAX
Output Frequency
N = 00 (
÷1)
N = 01 (
÷2)
N = 10 (
÷4)
N = 11 (
÷8)
200
100
50
25
400
200
100
50
MHz
DC
Output Duty Cycle
48
50
52
%
tr, tf
Output Rise/Fall Time
0.05
0.3
ns
20% to 80%
fS_CLOCK
Serial Interface Programming Clock Frequency(3)
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
10
MHz
tP,MIN
Minimum Pulse Width
(S_LOAD, P_LOAD)50
ns
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
ns
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
ns
tJIT(CC)
Cycle-to-Cycle Jitter
50
ps
N
≠ 8
tJIT(PER)
Period Jitter
50
ps
N
≠ 8
tLOCK
Maximum PLL Lock Time
10
ms
SSMfmod
Spread Spectrum Modulation Frequency
32
kHz
fXTAL = 16 MHz
SSMdev
Spread Spectrum Modulation Deviation
SS[3:0] = 0001
SS[3:0] = 1001
±0.30
-0.3
±0.5
-0.5
%
fout = 300 MHz
fXTAL = 16 MHz
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