- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄2099 > MPC92469AC (IDT, Integrated Device Technology Inc)IC SYNTHESIZER LVPECL 32-LQFP PDF資料下載
參數(shù)資料
| 型號： | MPC92469AC |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVPECL 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | 時(shí)鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 托盤 |
MPC92469 Data Sheet
400MHZ, LOW VOLTAGE, PECL CLOCK SYNTHESIZER W/SPREAD SPECTRUM
MPC92469 REVISION 4 FEBRUARY 6, 2013
3
2013 Integrated Device Technology, Inc.
(Top View)
Table 1. Pin Configurations
Pin
I/O
Default
Type
Function
XTAL_IN, XTAL_OUT
Analog
Crystal oscillator interface.
FOUT, FOUT
Output
LVPECL
Differential clock output.
TEST
Output
LVCMOS Test and device diagnosis output.
S_LOAD
Input
0
LVCMOS Serial configuration control input.
This inputs controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
P_LOAD
Input
1
LVCMOS Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive.
S_DATA
Input
0
LVCMOS Serial configuration data input.
S_CLOCK
Input
0
LVCMOS Serial configuration clock input.
M[8:0]
Input
1
LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
Input
1
LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD.
OE
Input
1
LVCMOS Output enable (active high).
The output enable is synchronous to the output clock to eliminate the possibility
of runt pulses on the FOUT output. OE = L low stops FOUT in the logic low state
(FOUT = L, FOUT = H).
GND
Supply
Ground
Negative power supply (GND).
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the
positive power supply for correct operation.
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply).
Table 2. Output Frequency Range and PLL Post-Divider N
N
Output Division
Output Frequency Range
N1
N0
0
1
200 – 400 MHz
0
1
2
100 – 200 MHz
1
0
4
50 – 100 MHz
1
8
25 – 50 MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC9315AC | IC PLL CLOCK GEN/DRIVER 32-LQFP |
| MPC9350AC | IC PLL CLOCK DRIVER LV 32-LQFP |
| MPC941AE | IC CLOCK BUFFER MUX 1:27 48-LQFP |
| MPC9443FAR2 | IC CLK BUFF DVDR MUX 3:16 48LQFP |
| MPC9446FAR2 | IC CLK BUFF DVDR MUX 2:10 32LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92469ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC9259 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER |
| MPC9259D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER |
| MPC9259FA | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER |
| MPC926508SD | 功能描述:IC NETWORKING CLK SOURCE 20-SSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。