參數(shù)資料
型號： MPC92439FN
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘產(chǎn)生/分配
英文描述： 900 MHz, OTHER CLOCK GENERATOR, PQCC28
封裝： PLASTIC, LCC-28
文件頁數(shù)： 9/13頁
文件大?。?/td> 840K
代理商： MPC92439FN
MPC92439
900MHZ, LOW VOLTAGE, LVPECL CLOCK SYNTHESIZER
IDT / ICS LVPECL CLOCK SYNTHESIZER
5
MPC92439 REV 3 JANUARY 7, 2008
Table 6. DC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (FREF_EXT, POWER_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
VIH
Input High Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.8
V
LVCMOS
IIN
Input Current(1)
1. Inputs have pull-down resistors affecting the input current.
±200
AVIN = VCC or GND
Differential Clock Output FOUT(2)
2. Outputs terminated 50
to VTT = VCC – 2V.
VOH
Output High Voltage
VCC–1.02
VCC–0.74
V
LVPECL
VOL
Output Low Voltage
VCC–1.95
VCC–1.60
V
LVPECL
Test and Diagnosis Output TEST
VOH
Output High Voltage
2.0
V
IOH = –0.8 mA
VOL
Output Low Voltage
0.55
V
IOL = 0.8 mA
Supply Current
ICC_PLL
Maximum PLL Supply Current
20
mA
VCC_PLL Pins
ICC
Maximum Supply Current
62
110
mA
All VCC Pins
Table 7. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal interface frequency range
10
20
MHz
fVCO
VCO frequency range(2)
400
900
MHz
fMAX
Output Frequency
N = 11 (
÷1)
N = 00 (
÷2)
N = 01 (
÷4)
N = 10 (
÷8)
400
200
100
50
900
450
225
112.5
MHz
PWR_DOWN = 0
fS_CLOCK
Serial Interface Programming Clock Frequency(3)
010
MHz
tP,MIN
Minimum Pulse Width
(S-LOAD, P_LOAD)50
ns
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.05
0.3
ns
20% to 80%
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
ns
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
ns
tJIT(CC)
Cycle-to-cycle jitter (RMS 1
σ)(4)
N=11 (÷1)
N=00 (÷2)
N=01 (÷4)
N=10 (÷8)
12
25
55
65
ps
tJIT(CC)
Period jitter (RMS 1
σ)(5)
N=11 (÷1)
N=00 (÷2)
N=01 (÷4)
N=10 (÷8)
13
23
36
40
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50
to VTT.
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
4. Maximum cycle jitter measured at the lowest VCO frequency. Figure 4 shows the cycle jitter vs. frequency characteristics
5. Maximum period jitter measured at the lowest VCO frequency. Figure 5 shows the period jitter vs. frequency characteristics
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