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參數(shù)資料
| 型號： | MPC9230FN |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 750 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 795K |
| 代理商： | MPC9230FN |
MPC9230 REVISION 8 MARCH 29, 2010
6
2010 Integrated Device Technology, Inc.
MPC9230 Data Sheet
800MHZ LOW VOLTAGE PECL CLOCK SYNTHESIZER
Table 8. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal Interface Frequency Range
10
20
MHz
fREF
FREF_EXT Reference Frequency Range
10
(fVCO,MAX÷M)4(2)
2. The maximum frequency on FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable PLL operation.
MHz
fVCO
VCO Frequency Range(3)
3. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL M ÷ 4.
800
1600
MHz
fMAX
Output Frequency
N = 11 (
÷1)
N = 00 (
÷2)
N = 01 (
÷4)
N = 10 (
÷8)
400
200
100
50
800
400
200
100
MHz
fS_CLOCK
Serial Interface Programming Clock Frequency(4)
4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used as test clock
in test mode 6. See APPLICATIONS INFORMATION for more details.
0
10
MHz
tP,MIN
Minimum Pulse Width
(S_LOAD, P_LOAD)
50
ns
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.05
0.3
ns
20% to 80%
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
ns
tH
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
ns
tJIT(CC)
Cycle-to-Cycle Jitter
N = 11 (
÷1)
N = 00 (
÷2)
N = 01 (
÷4)
N = 10 (
÷8)
30
35
45
55
80
90
130
160
ps
tJIT(PER)
Period Jitter
N = 11 (
÷1)
N = 00 (
÷2)
N = 01 (
÷4)
N = 10 (
÷8)
20
25
35
50
60
70
120
140
ps
tLOCK
Maximum PLL Lock Time
10
ms
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