
MPC862/857T/857DSL PowerQUICC Family Hardware Specifications, Rev. 3
34
Freescale Semiconductor
Bus Signal Timing
Figure 19 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM.
Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled
Cycles Timing
Figure 20 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
Figure 20. Asynchronous UPWAIT Negated Detection in UPM Handled
Cycles Timing
CLKOUT
CSx
UPWAIT
GPL_A[0:5],
GPL_B[0:5]
BS_A[0:3],
BS_B[0:3]
B37
B38
CLKOUT
CSx
UPWAIT
GPL_A[0:5],
GPL_B[0:5]
BS_A[0:3],
BS_B[0:3]
B37
B38