
MPC862/857T/857DSL PowerQUICC Family Hardware Specifications, Rev. 3
72
Freescale Semiconductor
Mechanical Data and Ordering Information
Figure 76 shows the MII serial management channel timing diagram.
Figure 76. MII Serial Management Channel Timing Diagram
14 Mechanical Data and Ordering Information
Table 33 provides information on the MPC862/857T/857DSL derivative devices.
Table 32. MII Serial Management Channel Timing
Num
Characteristic
Min
Max
Unit
M10
MII_MDC falling edge to MII_MDIO output invalid (minimum
propagation delay)
0—
ns
M11
MII_MDC falling edge to MII_MDIO output valid (max prop delay)
—
25
ns
M12
MII_MDIO (input) to MII_MDC rising edge setup
10
—
ns
M13
MII_MDIO (input) to MII_MDC rising edge hold
0
—
ns
M14
MII_MDC pulse width high
40%
60%
MII_MDC period
M15
MII_MDC pulse width low
40%
60%
MII_MDC period
Table 33. MPC862/857T/857DSL Derivatives
Device
Number
of
SCCs 1
Ethernet
Support
Multi-Channel
HDLC Support
ATM Support
Cache Size
Instruction
Data
MPC862T
Four
10/100 Mbps
Yes
4 Kbytes
MPC862P
Four
10/100 Mbps
Yes
16 Kbytes
8 Kbytes
M11
MII_MDC (output)
MII_MDIO (output)
M12
M13
MII_MDIO (input)
M10
M14
MM15