Input leakage current, V
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MPC860SRCVR66D4
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 3/78闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MPU POWERQUICC 66MHZ 357PBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 44
绯诲垪锛� MPC8xx
铏曠悊鍣ㄩ鍨嬶細 32-浣� MPC8xx PowerQUICC
閫熷害锛� 66MHz
闆诲锛� 3.3V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 357-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 357-PBGA锛�25x25锛�
鍖呰锛� 鎵樼洡
MPC860 PowerQUICC Family Hardware Specifications, Rev. 9
Freescale Semiconductor
11
DC Characteristics
Input leakage current, Vin = 3.6 V (except TMS, TRST,
DSCK, and DSDI pins)
IIn
鈥�10
A
Input leakage current, Vin = 0 V (except TMS, TRST,
DSCK, and DSDI pins)
IIn
鈥�10
A
Input capacitance2
Cin
鈥�20
pF
Output high voltage, IOH = 鈥�2.0 mA, VDDH =3.0 V
(except XTAL, XFC, and open-drain pins)
VOH
2.4
鈥�
V
Output low voltage
IOL = 2.0 mA, CLKOUT
IOL = 3.2 mA
3
IOL = 5.3 mA
4
IOL = 7.0 mA, TXD1/PA14, TXD2/PA12
IOL = 8.9 mA, TS, TA, TEA, BI, BB, HRESET, SRESET
VOL
鈥�0.5
V
1 V
IL(max) for the I
2C interface is 0.8 V rather than the 1.5 V as specified in the I2C standard.
2 Input capacitance is periodically sampled.
3 A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1),
IP_B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3,
RXD1/PA15, RXD2/PA13, L1TXDB/PA11, L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7,
BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/
L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, L1TCLKB/TOUT4/CLK8/PA0, REJCT1/SPISEL/PB31, SPICLK/
PB30,SPIMOSI/PB29, BRGO4/SPIMISO/PB28, BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26, SMTXD1/PB25, SMRXD1/
PB24, SMSYN1/SDACK1/PB23, SMSYN2/SDACK2/PB22, SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20, L1ST1/
RTS1/PB19, L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16, BRGO3/PB15, RSTRT1/PB14, L1ST1/RTS1/
DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12, CTS1/PC11, TGATE1/CD1/PC10,
CTS2/PC9, TGATE2/CD2/PC8, SDACK2/L1TSYNCB/PC7, L1RSYNCB/PC6, SDACK1/L1TSYNCA/PC5, L1RSYNCA/PC4,
PD15, PD14, PD13, PD12, PD11, PD10, PD9, PD8, PD5, PD6, PD7, PD4, PD3, MII_MDC, MII_TX_ER, MII_EN, MII_MDIO,
and MII_TXD[0:3]
4 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/IOWR,
WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/
CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1),
OP2/MODCK1/STS, OP3/MODCK2/DSDO, and BADDR(28:30)
Table 6. DC Electrical Specifications (continued)
Characteristic
Symbol
Min
Max
Unit
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
XPC8240LVV200E IC MPU INTEGRATED 200MHZ 352TBGA
MPC8360CZUAJDGA IC MPU POWERQUICC II PRO 740TBGA
MPC8360CVVAJDGA IC MPU POWERQUICC II PRO 740TBGA
MPC862TCZQ50B IC MPU PWRQUICC 80MHZ 357-PBGA
MPC862TCVR50B IC MPU POWERQUICC 50MHZ 357PBGA
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
MPC860SRCZQ5 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪: 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:
MPC860SRCZQ50D4 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU POWER QUICC RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MPC860SRCZQ66D4 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU POWER QUICC RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MPC860SR-PHY 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU PQ PHY BOARD RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MPC860SRVR50D4 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU POWER QUICC RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324