
MPC860 PowerQUICC Family Hardware Specifications, Rev. 8
68
Freescale Semiconductor
FEC Electrical Characteristics
13.2
MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency – 1%.
Table 30 provides information on the MII transmit signal timing.
Figure 73 shows the MII transmit signal timing diagram.
Figure 73. MII Transmit Signal Timing Diagram
Table 30. MII Transmit Signal Timing
Num
Characteristic
Min
Max
Unit
M5
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid
5
—
ns
M6
MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid
—
25
M7
MII_TX_CLK pulse width high
35
65%
MII_TX_CLK
period
M8
MII_TX_CLK pulse width low
35%
65%
MII_TX_CLK
period
M6
MII_TX_CLK (Input)
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M5
M7
M8
RMII_REFCLK