參數(shù)資料
型號: MPC859TZP100
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA357
封裝: PLASTIC, BGA-357
文件頁數(shù): 70/92頁
文件大?。?/td> 1018K
代理商: MPC859TZP100
72
MPC866/859 Hardware Specications
MOTOROLA
FEC Electrical Characteristics
14
FEC Electrical Characteristics
This section provides the AC electrical specications for the fast Ethernet controller (FEC). Note that the
timing specications for the MII signals are independent of system clock frequency (part speed
designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 or 3.3
V.
14.1
MII Receive Signal Timing (MII_RXD [3:0], MII_RX_DV,
MII_RX_ER, MII_RX_CLK)
The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25 MHz + 1%. There is no
minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_RX_CLK frequency – 1%. Table 33 shows the timings for MII receive signal.
Figure 74 shows the timings for MII receive signal.
Figure 74. MII Receive Signal Timing Diagram
14.2
MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,
MII_TX_ER, MII_TX_CLK)
The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz +1%. There is
no minimum frequency requirement. In addition, the processor clock frequency must exceed the
MII_TX_CLK frequency - 1%.
Table 33. MII Receive Signal Timing
Num
Characteristic
Min
Max
Unit
M1
MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup
5
ns
M2
MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold
5
ns
M3
MII_RX_CLK pulse width high
35%
65%
MII_RX_CLK period
M4
MII_RX_CLK pulse width low
35%
65%
MII_RX_CLK period
M1
M2
MII_RX_CLK (input)
MII_RXD[3:0] (inputs)
MII_RX_DV
MII_RX_ER
M3
M4
相關PDF資料
PDF描述
MPC866PZP133 32-BIT, 133 MHz, RISC PROCESSOR, PBGA357
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