參數(shù)資料
型號: MPC8572VTAULB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 137/138頁
文件大?。?/td> 1502K
代理商: MPC8572VTAULB
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
98
Freescale Semiconductor
Serial RapidIO
17.7
Receiver Eye Diagrams
For each baud rate at which an LP-Serial receiver is specified to operate, the receiver shall meet the
corresponding Bit Error Rate specification (Table 69, Table 70, Table 71) when the eye pattern of the
receiver test signal (exclusive of sinusoidal jitter) falls entirely within the unshaded portion of the Receiver
Input Compliance Mask shown in Figure 60 with the parameters specified in Table 72. The eye pattern of
the receiver test signal is measured at the input pins of the receiving device with the device replaced with
a 100-
Ω +/– 5% differential resistive load.
Figure 60. Receiver Input Compliance Mask
17.8
Measurement and Test Requirements
Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause
47 of IEEE 802.3ae-2002, the measurement and test requirements defined here are similarly guided by
Table 72. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter
Receiver Type
VDIFFmin (mV) VDIFFmax (mV)
A (UI)
B (UI)
1.25 GBaud
100
800
0.275
0.400
2.5 GBaud
100
800
0.275
0.400
3.125 GBaud
100
800
0.275
0.400
1
0
VDIFF max
-VDIFF max
VDIFF min
-VDIFF min
Time (UI)
Recei
v
er
Di
ff
e
rent
ia
l
Input
V
o
lt
age
0
AB
1-B
1-A
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