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| 型號： | MPC8572EPXAVND |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023 |
| 封裝： | 33 X 33 MM, PLASTIC, FCBGA-1023 |
| 文件頁數(shù)： | 96/138頁 |
| 文件大?。?/td> | 1502K |
| 代理商： | MPC8572EPXAVND |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
60
Freescale Semiconductor
Local Bus Controller (eLBC)
LALE output transition to LAD/LDP output transition
(LATCH hold time)
tLBOTOT
1.5
—
ns
6
Local bus clock to output valid (except LAD/LDP and
LALE)
tLBKLOV1
—–0.3
ns
Local bus clock to data valid for LAD/LDP
tLBKLOV2
—–0.1
ns
4
Local bus clock to address valid for LAD
tLBKLOV3
—0.0
ns
4
Local bus clock to LALE assertion
tLBKLOV4
—0.0
ns
4
Output hold from local bus clock (except LAD/LDP
and LALE)
tLBKLOX1
–3.3
—
ns
4
Output hold from local bus clock for LAD/LDP
tLBKLOX2
–3.3
—
ns
4
Local bus clock to output high Impedance (except
LAD/LDP and LALE)
tLBKLOZ1
—0.2
ns
7
Local bus clock to output high impedance for
LAD/LDP
tLBKLOZ2
—0.2
ns
7
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for
clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to
the output (O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes LCLK
by tLBKHKT.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at BVDD/2.
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 x BVDD of the signal
in question for 3.3-V signaling levels.
5. Input timings are measured at the pin.
6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through
the component pin is less than or equal to the leakage current specification.
Table 51. Local Bus General Timing Parameters—PLL Bypassed (continued)
At recommended operating conditions with BVDD of 3.3 V ± 5%
Parameter
Symbol 1
Min
Max
Unit
Notes
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