
HDLC, BISYNC, Transparent, and Synchronous UART Interfaces
MPC8569E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 0
Freescale Semiconductor
75
The following figure shows the MII management AC timing diagram.
Figure 34. MII Management Interface Timing Diagram
2.8
HDLC, BISYNC, Transparent, and Synchronous UART Interfaces
This section describes the DC and AC electrical specifications for the high level data link control (HDLC), BISYNC,
transparent, and synchronous UART interfaces of the MPC8569E.
2.8.1
HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical
Characteristics
The following table provides the DC electrical characteristics for the HDLC, BISYNC, Transparent, and synchronous UART
interfaces.
Table 43. HDLC, BISYNC, and Transparent DC Electrical Characteristics
For recommended operating conditions, see
Table 3Parameter
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
2—
V
1
Input low voltage
VIL
—0.8
V
1
Input current (OVIN = 0 V or OVIN = OVDD)IIN
—±40
μA2
Output high voltage (OVDD = min, IOH = –2 mA)
VOH
2.4
—
V
—
Output low voltage (OVDD = min, IOL = 2 mA)
VOL
—0.4
V
—
Note:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3. 2. The symbol OVIN represents the input voltage of the supply. It is referenced in Table 3. MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDKHDX
MDIO
(Input)
(Output)
tMDDVKH