參數(shù)資料
型號: MPC8568VTAUJJ
廠商: Freescale Semiconductor
文件頁數(shù): 135/139頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標準包裝: 24
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
95
UTOPIA/POS
Figure 62 provides the AC test load for the Utopia.
Figure 62. Utopia AC Test Load
Figure 63 through Figure 64 represent the AC timing from Table 74. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 63 shows the Utopia timing with external clock.
Figure 63. Utopia AC Timing (External Clock) Diagram
Utopia inputs—Internal clock input setup time
tUIIVKH
6—
ns
Utopia inputs—External clock input setup time
tUEIVKH
4—
ns
Utopia inputs—Internal clock input Hold time
tUIIXKH
0—
ns
Utopia inputs—External clock input hold time
tUEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tUIKHOX symbolizes the Utopia outputs internal timing (UI) for the time tUtopia memory clock reference (K) goes
from the high state (H) until outputs (O) are invalid (X).
Table 74. Utopia AC Timing Specifications 1 (continued)
Characteristic
Symbol 2
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
UtopiaCLK (input)
tUEIXKH
tUEIVKH
tUEKHOV
Input Signals:
Utopia
Output Signals:
Utopia
tUEKHOX
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