參數(shù)資料
型號： MPC8568EVTAUJJ
廠商： Freescale Semiconductor
文件頁數(shù)： 116/139頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 1023-PBGA
標準包裝： 24
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.333GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應商設備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
78
Freescale Semiconductor
Serial RapidIO
Figure 51. Compliance Test/Measurement Load
15 Serial RapidIO
This section describes the DC and AC electrical specifications for the RapidIO interface of the
MPC8568E, for the LP-Serial physical layer. The electrical specifications cover both single and
multiple-lane links. Two transmitters (short run and long run) and a single receiver are specified for each
of three baud rates, 1.25, 2.50, and 3.125 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board interconnect to
driving two connectors across a backplane. A single receiver specification is given that will accept signals
from both the short run and long run transmitter specifications.
The short run transmitter should be used mainly for chip-to-chip connections on either the same printed
circuit board or across a single connector. This covers the case where connections are made to a mezzanine
(daughter) card. The minimum swings of the short run specification reduce the overall power used by the
transceivers.
The long run transmitter specifications use larger voltage swings that are capable of driving signals across
backplanes. This allows a user to drive signals across two connectors and a backplane. The specifications
allow a distance of at least 50 cm at all baud rates.
All unit intervals are specified with a tolerance of +/– 100 ppm. The worst case frequency difference
between any transmit and receive clock will be 200 ppm.
To ensure interoperability between drivers and receivers of different vendors and technologies, AC
coupling at the receiver input must be used.
15.1
DC Requirements for Serial RapidIO SD_REF_CLK and
SD_REF_CLK
For more information, see Section 13.2, “SerDes Reference Clocks.”
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