
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
92
Freescale Semiconductor
TDM/SI
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 58 shows the SPI timing in Slave mode (external clock).
Figure 58. SPI AC Timing in Slave mode (External Clock) Diagram
Figure 59 shows the SPI timing in Master mode (internal clock).
Figure 59. SPI AC Timing in Master mode (Internal Clock) Diagram
19 TDM/SI
This section describes the DC and AC electrical specifications for the time-division-multiplexed and serial
interface of the MPC8568E.
19.1
TDM/SI DC Electrical Characteristics
Table 71 provides the DC electrical characteristics for the MPC8568E TDM/SI.
Table 71. TDM/SI DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Output high voltage
VOH
IOH = –2.0 mA
2.4
—
V
Output low voltage
VOL
IOL = 3.2 mA
—
0.5
V
Input high voltage
VIH
—2.0
OVDD+0.3
V
SPICLK (input)
tNEIXKH
tNEIVKH
tNEKHOV
Input Signals:
SPIMOSI
(See Note)
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
SPICLK (output)
tNIIXKH
tNIKHOV
Input Signals:
SPIMISO
(See Note)
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
tNIIVKH