參數(shù)資料
型號: MPC8560VTAQFC
廠商: Freescale Semiconductor
文件頁數(shù): 73/108頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 783FCPBGA
標準包裝: 36
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 783-FCPBGA(29x29)
包裝: 托盤
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
67
RapidIO
The compliance of receiver input signals RD[0:15] and RFRAME with their minimum data valid window
(DV) specification shall be determined by generating an eye pattern for each of the data signals and
comparing the eye pattern of each data signal with the RapidIO receive mask shown in Figure 46. The
value of X2 used to construct the mask shall be (1 – DVmin)/2. The ±100 mV minimum data valid and
±600 mV maximum input voltage values are from the DC specification. A signal is compliant with the data
valid window specification if and only if the receive mask can be positioned on the signal’s eye pattern
such that the eye pattern falls entirely within the unshaded portion of the mask.
Figure 46. RapidIO Receive Mask
The eye pattern for a data signal is generated by making a large number of recordings of the signal and
then overlaying the recordings. The number of recordings used to generate the eye shall be large enough
that further increasing the number of recordings used does not cause the resulting eye pattern to change
from one that complies with the RapidIO receive mask to one that does not. Each data signal in the
interface shall be carrying random or pseudo-random data when the recordings are made. If
pseudo-random data is used, the length of the pseudo-random sequence (repeat length) shall be long
Table 53. RapidIO Receiver AC Timing Specifications—1 Gbps Data Rate
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Duty cycle of the clock input
DC
47
53
%
1, 5
Data valid
DV
425
ps
2
Allowable static skew between any two data inputs
within a 8-/9-bit group
tDPAIR
—300
ps
3
Allowable static skew of data inputs to associated clock
tSKEW,PAIR
–200
200
ps
4
Notes:
1.Measured at VID = 0 V.
2.Measured using the RapidIO receive mask shown in Figure 46.
3.See Figure 49.
5.Guaranteed by design.
X2
600
0
100
–100
–600
1–X2
DV
V
ID
(m
V
)
Time (UI)
01
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